📄 mx1_def.h
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#define AITC_INTTYPEH (AITC_BASE_ADDR+0x18)
#define AITC_INTTYPEL (AITC_BASE_ADDR+0x1C)
#define AITC_NIPRIORITY7 (AITC_BASE_ADDR+0x20)
#define AITC_NIPRIORITY6 (AITC_BASE_ADDR+0x24)
#define AITC_NIPRIORITY5 (AITC_BASE_ADDR+0x28)
#define AITC_NIPRIORITY4 (AITC_BASE_ADDR+0x2C)
#define AITC_NIPRIORITY3 (AITC_BASE_ADDR+0x30)
#define AITC_NIPRIORITY2 (AITC_BASE_ADDR+0x34)
#define AITC_NIPRIORITY1 (AITC_BASE_ADDR+0x38)
#define AITC_NIPRIORITY0 (AITC_BASE_ADDR+0x3C)
#define AITC_NIVECSR (AITC_BASE_ADDR+0x40)
#define AITC_FIVECSR (AITC_BASE_ADDR+0x44)
#define AITC_INTSRCH (AITC_BASE_ADDR+0x48)
#define AITC_INTSRCL (AITC_BASE_ADDR+0x4C)
#define AITC_INTFRCH (AITC_BASE_ADDR+0x50)
#define AITC_INTFRCL (AITC_BASE_ADDR+0x54)
#define AITC_NIPNDH (AITC_BASE_ADDR+0x58)
#define AITC_NIPNDL (AITC_BASE_ADDR+0x5C)
#define AITC_FIPNDH (AITC_BASE_ADDR+0x60)
#define AITC_FIPNDL (AITC_BASE_ADDR+0x64)
#define INTCNTL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x00))
#define NIMASK (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x04))
#define INTENNUM (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x08))
#define INTDISNUM (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x0C))
#define INTENABLEH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x10))
#define INTENABLEL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x14))
#define INTTYPEH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x18))
#define INTTYPEL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x1C))
#define NIPRIORITY7 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x20))
#define NIPRIORITY6 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x24))
#define NIPRIORITY5 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x28))
#define NIPRIORITY4 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x2C))
#define NIPRIORITY3 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x30))
#define NIPRIORITY2 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x34))
#define NIPRIORITY1 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x38))
#define NIPRIORITY0 (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x3C))
#define NIVECSR (*(volatile int *) (AITC_BASE_ADDR + 0x40))
#define FIVECSR (*(volatile int *) (AITC_BASE_ADDR + 0x44))
#define INTSRCH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x48))
#define INTSRCL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x4C))
#define INTFRCH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x50))
#define INTFRCL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x54))
#define NIPNDH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x58))
#define NIPNDL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x5C))
#define FIPNDH (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x60))
#define FIPNDL (*(volatile unsigned int *) (AITC_BASE_ADDR + 0x64))
//
// ;---------------------------------------;
// ; ASP Karen move ;
// ; $0021_5000 to $0021_5FFF ;
// ;---------------------------------------;
//#define ASP_BASE_ADDR 0xf0215000
//#define ASP_PADFIFO (ASP_BASE_ADDR+0x00)
//#define ASP_VADFIFO (ASP_BASE_ADDR+0x04)
//#define ASP_VDAFIFO (ASP_BASE_ADDR+0x08)
//#define ASP_VADCOEF (ASP_BASE_ADDR+0x0C)
//#define ASP_ACNTLCR (ASP_BASE_ADDR+0x10)
//#define ASP_PSMPLRG (ASP_BASE_ADDR+0x14)
//#define ASP_ICNTLR (ASP_BASE_ADDR+0x18)
//#define ASP_ISTATR (ASP_BASE_ADDR+0x1C)
//#define ASP_VADGAIN (ASP_BASE_ADDR+0x20)
//#define ASP_VDAGAIN (ASP_BASE_ADDR+0x24)
//#define ASP_VDACOEF (ASP_BASE_ADDR+0x28)
//#define ASP_CLKDIV (ASP_BASE_ADDR+0x2C)
//#define ASP_CMPCNTL (ASP_BASE_ADDR+0x30)
//#define ASP_PTRREG (ASP_BASE_ADDR+0x34)
//
// ;---------------------------------------;
// ; BOOT ROM ;
// ;---------------------------------------;
#define BOOTROM_ADDR_BOT 0x00000000
#define BOOTROM_PHY_SIZE 0x0000028C
#define BOOTROM_ASS_SIZE 0x00100000
//
// ;---------------------------------------;
// ; BTA_WRAPPER ;
// ; $0021_6000 to $0021_6FFF ;
// ;---------------------------------------;
// ; Sequencer
#define BTA_BASE_ADDR 0xf0216000
#define BTA_COMMAND BTA_BASE_ADDR
#define BTA_STATUS BTA_BASE_ADDR
#define BTA_PACKETHEAD (BTA_BASE_ADDR+0x04)
#define BTA_PAYLOADHEAD (BTA_BASE_ADDR+0x08)
//
// ; BT clocks
#define BTA_NATIVECNT (BTA_BASE_ADDR+0x0C)
#define BTA_ESTCNT (BTA_BASE_ADDR+0x10)
#define BTA_OFFSETCNT (BTA_BASE_ADDR+0x14)
#define BTA_NATIVECLK_L (BTA_BASE_ADDR+0x18)
#define BTA_NATIVECLK_H (BTA_BASE_ADDR+0x1C)
#define BTA_ESTCLK_L (BTA_BASE_ADDR+0x20)
#define BTA_ESTCLK_H (BTA_BASE_ADDR+0x24)
#define BTA_OFFSETCLK_L (BTA_BASE_ADDR+0x28)
#define BTA_OFFSETCLK_H (BTA_BASE_ADDR+0x2C)
//
// ; BT pipeline
#define BTA_HECCRC (BTA_BASE_ADDR+0x30)
#define BTA_WHITE (BTA_BASE_ADDR+0x34)
#define BTA_ENCRYPT (BTA_BASE_ADDR+0x38)
//
// ; Radio Control
#define BTA_CORR_TIME (BTA_BASE_ADDR+0x40)
#define BTA_RF_GPO (BTA_BASE_ADDR+0x48)
#define BTA_RSSI (BTA_BASE_ADDR+0x4C)
#define BTA_TIME_AB (BTA_BASE_ADDR+0x50)
#define BTA_TIME_CD (BTA_BASE_ADDR+0x54)
#define BTA_PWM_TX (BTA_BASE_ADDR+0x58)
#define BTA_RF_CTRL (BTA_BASE_ADDR+0x5C)
#define BTA_RF_STATUS (BTA_BASE_ADDR+0x5C)
#define BTA_RX_TIME (BTA_BASE_ADDR+0x60)
#define BTA_TX_TIME (BTA_BASE_ADDR+0x64)
// ; Bit Reverse
#define BTA_WORD_REV (BTA_BASE_ADDR+0x178)
#define BTA_BYTE_REV (BTA_BASE_ADDR+0x17C)
//
// ; Timer
#define BTA_TIMER (BTA_BASE_ADDR+0x68)
//
// ; Correlator
#define BTA_THRESHOLD (BTA_BASE_ADDR+0x6C)
#define BTA_CORR_MAX (BTA_BASE_ADDR+0x6C)
#define BTA_SYNCHWORD_0 (BTA_BASE_ADDR+0x70)
#define BTA_SYNCHWORD_1 (BTA_BASE_ADDR+0x74)
#define BTA_SYNCHWORD_2 (BTA_BASE_ADDR+0x78)
#define BTA_SYNCHWORD_3 (BTA_BASE_ADDR+0x7C)
//
// ; BitBUF
#define BTA_BUF_WORD_0 (BTA_BASE_ADDR+0x80)
#define BTA_BUF_WORD_1 (BTA_BASE_ADDR+0x84)
#define BTA_BUF_WORD_2 (BTA_BASE_ADDR+0x88)
#define BTA_BUF_WORD_3 (BTA_BASE_ADDR+0x8C)
#define BTA_BUF_WORD_4 (BTA_BASE_ADDR+0x90)
#define BTA_BUF_WORD_5 (BTA_BASE_ADDR+0x94)
#define BTA_BUF_WORD_6 (BTA_BASE_ADDR+0x98)
#define BTA_BUF_WORD_7 (BTA_BASE_ADDR+0x9C)
#define BTA_BUF_WORD_8 (BTA_BASE_ADDR+0xA0)
#define BTA_BUF_WORD_9 (BTA_BASE_ADDR+0xA4)
#define BTA_BUF_WORD_10 (BTA_BASE_ADDR+0xA8)
#define BTA_BUF_WORD_11 (BTA_BASE_ADDR+0xAC)
#define BTA_BUF_WORD_12 (BTA_BASE_ADDR+0xB0)
#define BTA_BUF_WORD_13 (BTA_BASE_ADDR+0xB4)
#define BTA_BUF_WORD_14 (BTA_BASE_ADDR+0xB8)
#define BTA_BUF_WORD_15 (BTA_BASE_ADDR+0xBC)
#define BTA_BUF_WORD_16 (BTA_BASE_ADDR+0xC0)
#define BTA_BUF_WORD_17 (BTA_BASE_ADDR+0xC4)
#define BTA_BUF_WORD_18 (BTA_BASE_ADDR+0xC8)
#define BTA_BUF_WORD_19 (BTA_BASE_ADDR+0xCC)
#define BTA_BUF_WORD_20 (BTA_BASE_ADDR+0xD0)
#define BTA_BUF_WORD_21 (BTA_BASE_ADDR+0xD4)
#define BTA_BUF_WORD_22 (BTA_BASE_ADDR+0xD8)
#define BTA_BUF_WORD_23 (BTA_BASE_ADDR+0xDC)
#define BTA_BUF_WORD_24 (BTA_BASE_ADDR+0xE0)
#define BTA_BUF_WORD_25 (BTA_BASE_ADDR+0xE4)
#define BTA_BUF_WORD_26 (BTA_BASE_ADDR+0xE8)
#define BTA_BUF_WORD_27 (BTA_BASE_ADDR+0xEC)
#define BTA_BUF_WORD_28 (BTA_BASE_ADDR+0xF0)
#define BTA_BUF_WORD_29 (BTA_BASE_ADDR+0xF4)
#define BTA_BUF_WORD_30 (BTA_BASE_ADDR+0xF8)
#define BTA_BUF_WORD_31 (BTA_BASE_ADDR+0xFC)
//
// ; Wakeup
#define BTA_WU_1 (BTA_BASE_ADDR+0x100)
#define BTA_WU_2 (BTA_BASE_ADDR+0x104)
#define BTA_WU_3 (BTA_BASE_ADDR+0x108)
#define BTA_WU_DELTA3 (BTA_BASE_ADDR+0x108)
#define BTA_WU_4 (BTA_BASE_ADDR+0x10C)
#define BTA_WU_DELTA4 (BTA_BASE_ADDR+0x10C)
#define BTA_WU_CTRL (BTA_BASE_ADDR+0x110)
#define BTA_WU_STATUS (BTA_BASE_ADDR+0x110)
#define BTA_WU_COUNT (BTA_BASE_ADDR+0x114)
//
// ; Clock control
#define BTA_CLK_CTRL (BTA_BASE_ADDR+0x118)
//
// ; SPI
#define BTA_SPI_WORD_0 (BTA_BASE_ADDR+0x120)
#define BTA_SPI_WORD_1 (BTA_BASE_ADDR+0x124)
#define BTA_SPI_WORD_2 (BTA_BASE_ADDR+0x128)
#define BTA_SPI_WORD_3 (BTA_BASE_ADDR+0x12C)
#define BTA_SPI_WADDR (BTA_BASE_ADDR+0x130)
#define BTA_SPI_RADDR (BTA_BASE_ADDR+0x134)
#define BTA_SPI_CTRL (BTA_BASE_ADDR+0x138)
#define BTA_SPI_STATUS (BTA_BASE_ADDR+0x138)
//
// ; Frequency Hopping
#define BTA_HOPWORDS_0 (BTA_BASE_ADDR+0x140)
#define BTA_FREQ_OUT (BTA_BASE_ADDR+0x140)
#define BTA_HOPWORDS_1 (BTA_BASE_ADDR+0x144)
#define BTA_HOPWORDS_2 (BTA_BASE_ADDR+0x148)
#define BTA_HOPWORDS_3 (BTA_BASE_ADDR+0x14C)
#define BTA_HOPWORDS_4 (BTA_BASE_ADDR+0x150)
//
// ; Interrupt
#define BTA_INTERRUPT (BTA_BASE_ADDR+0x160)
//
// ; MLSE
#define BTA_SYNC_METRIC (BTA_BASE_ADDR+0x170)
#define BTA_SYNC_FC (BTA_BASE_ADDR+0x174)
//
// ;---------------------------------------;
// ; Clock & Reset (CRM) ;
// ; $0021_B000 to $0021_BFFF ;
// ;---------------------------------------;
#define CRM_BASE_ADDR 0xf021B000
#define CRM_CSCR CRM_BASE_ADDR // ; Clock Source Control Reg
#define CRM_MPCTL0 (CRM_BASE_ADDR+0x04) // ; MCU PLL Control Reg
#define CRM_MPCTL1 (CRM_BASE_ADDR+0x08) // ; MCU PLL & System Clk Ctl Reg
#define CRM_UPCTL0 (CRM_BASE_ADDR+0x0C) // ; USB PLL Control Reg 0
#define CRM_UPCTL1 (CRM_BASE_ADDR+0x10) // ; USB PLL Control Reg 1
#define CRM_PCDR (CRM_BASE_ADDR+0x20) // ; Perpheral Clock Divider Reg
//
#define CRM_RSR (CRM_BASE_ADDR+0x800) // ; Reset Source Reg
#define CRM_SIDR (CRM_BASE_ADDR+0x804) // ; Silicon ID Reg
#define CRM_FMCR (CRM_BASE_ADDR+0x808) // ; Functional Muxing Control Reg
#define CRM_GPCR (CRM_BASE_ADDR+0x80C) // ; Global Control Reg
// ;---------------------------------------;
// ; CSI
// ; $0022_4000 to $0022_4FFF ;
// ;---------------------------------------;
#define CSI_BASE_ADDR 0xf0224000
#define CSI_CTRL_REG1 (CSI_BASE_ADDR+0x00)
#define CSI_CTRL_REG2 (CSI_BASE_ADDR+0x04)
#define CSI_STS_REG (CSI_BASE_ADDR+0x08)
#define CSI_STAT_FIFO (CSI_BASE_ADDR+0x0C)
#define CSI_RX_FIFO (CSI_BASE_ADDR+0x10)
//
// ;---------------------------------------;
// ; CSPI ;
// ; $0021_3000 to $0021_3FFF ;
// ;---------------------------------------;
#define CSPI_BASE_ADDR 0xf0213000
#define CSPI_SPIRXD CSPI_BASE_ADDR
#define CSPI_SPITXD (CSPI_BASE_ADDR+0x04)
#define CSPI_SPICONT1 (CSPI_BASE_ADDR+0x08)
#define CSPI_INTCS (CSPI_BASE_ADDR+0x0C)
#define CSPI_SPITEST (CSPI_BASE_ADDR+0x10)
#define CSPI_SPISPCR (CSPI_BASE_ADDR+0x14)
#define CSPI_SPIDMA (CSPI_BASE_ADDR+0x18)
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