cnt10.vhd

多功能时钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk,clr,en:in std_logic;
     q:buffer std_logic_vector(3 downto 0);
     c10:out std_logic);
end;
architecture one of cnt10 is 
     begin
        process(clk,clr)
          begin
if clr='1' then q<="0000";
elsif clk'event and clk='1' then
if en='1' then
 if q<9 then q<=q+1;
else q<="0000";
end if;
end if;
end if;
end process;
process(q,clk)
begin
  if clk'event and clk='1' then
  if q="1001" then
     c10<='1';
else c10<='0';
end if;
end if;
end process;
end;