cnt3.vhd

来自「多功能时钟」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt3 is
port(clk,clr,en:in std_logic;
     q:buffer std_logic_vector(2 downto 0);
     c3:out std_logic);
end;
architecture one of cnt3 is 
     begin
        process(clk,clr)
          begin
if clr='1' then q<="000";
elsif clk'event and clk='1' then
if en='1' then
 if q<2 then q<=q+1;
else q<="000";
end if;
end if;
end if;
end process;
process(q,clk)
begin
if clk'event and clk='1' then
if q="010" then
     c3<='1';
else c3<='0';
end if;
end if;
end process;
end;