count1024.vhd

来自「多功能时钟」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count1024 is
port(clk:in std_logic;
          c1024:out std_logic);
end;
architecture one of count1024 is 
signal q: std_logic_vector(9 downto 0);
  
   begin
        process(clk)
          begin
if clk'event and clk='1' then
 if q<1023 then q<=q+1;
else q<="0000000000";
end if;
end if;
end process;
c1024<=q(9);
end;