📄 count1024.rpt
字号:
- 8 - B 07 DFFE + 0 2 0 1 q4 (:8)
- 6 - B 07 DFFE + 0 3 0 1 q3 (:9)
- 7 - B 07 DFFE + 0 2 0 2 q2 (:10)
- 5 - B 07 DFFE + 0 2 0 1 q1 (:11)
- 1 - B 07 DFFE + 0 0 0 2 q0 (:12)
- 1 - B 02 OR2 0 4 0 7 :54
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\multiclock\count1024.rpt
count1024
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\multiclock\count1024.rpt
count1024
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 clk
Device-Specific Information: g:\multiclock\count1024.rpt
count1024
** EQUATIONS **
clk : INPUT;
-- Node name is 'c1024'
-- Equation name is 'c1024', type is output
c1024 = q9;
-- Node name is ':12' = 'q0'
-- Equation name is 'q0', location is LC1_B7, type is buried.
q0 = DFFE(!q0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':11' = 'q1'
-- Equation name is 'q1', location is LC5_B7, type is buried.
q1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC1_B2 & q0 & !q1
# _LC1_B2 & !q0 & q1;
-- Node name is ':10' = 'q2'
-- Equation name is 'q2', location is LC7_B7, type is buried.
q2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC1_B2 & !_LC3_B7 & q2
# _LC1_B2 & _LC3_B7 & !q2;
-- Node name is ':9' = 'q3'
-- Equation name is 'q3', location is LC6_B7, type is buried.
q3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC1_B2 & !q2 & q3
# _LC1_B2 & !_LC3_B7 & q3
# _LC1_B2 & _LC3_B7 & q2 & !q3;
-- Node name is ':8' = 'q4'
-- Equation name is 'q4', location is LC8_B7, type is buried.
q4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC1_B2 & !_LC4_B7 & q4
# _LC1_B2 & _LC4_B7 & !q4;
-- Node name is ':7' = 'q5'
-- Equation name is 'q5', location is LC4_B2, type is buried.
q5 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC1_B2 & !_LC2_B7 & q5
# _LC1_B2 & _LC2_B7 & !q5;
-- Node name is ':6' = 'q6'
-- Equation name is 'q6', location is LC3_B2, type is buried.
q6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC1_B2 & !q5 & q6
# _LC1_B2 & !_LC2_B7 & q6
# _LC1_B2 & _LC2_B7 & q5 & !q6;
-- Node name is ':5' = 'q7'
-- Equation name is 'q7', location is LC5_B2, type is buried.
q7 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC1_B2 & !_LC2_B2 & q7
# _LC1_B2 & _LC2_B2 & !q7;
-- Node name is ':4' = 'q8'
-- Equation name is 'q8', location is LC6_B2, type is buried.
q8 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !q7 & q8
# !_LC2_B2 & q8
# _LC2_B2 & q7 & !q8;
-- Node name is ':3' = 'q9'
-- Equation name is 'q9', location is LC8_B2, type is buried.
q9 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !q7 & q9
# !_LC2_B2 & q9
# !q8 & q9
# _LC2_B2 & q7 & q8 & !q9;
-- Node name is '|LPM_ADD_SUB:131|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B7', type is buried
!_LC3_B7 = _LC3_B7~NOT;
_LC3_B7~NOT = LCELL( _EQ010);
_EQ010 = !q0
# !q1;
-- Node name is '|LPM_ADD_SUB:131|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B7', type is buried
!_LC4_B7 = _LC4_B7~NOT;
_LC4_B7~NOT = LCELL( _EQ011);
_EQ011 = !q3
# !q2
# !_LC3_B7;
-- Node name is '|LPM_ADD_SUB:131|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B7', type is buried
!_LC2_B7 = _LC2_B7~NOT;
_LC2_B7~NOT = LCELL( _EQ012);
_EQ012 = !q4
# !_LC4_B7;
-- Node name is '|LPM_ADD_SUB:131|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B2', type is buried
!_LC2_B2 = _LC2_B2~NOT;
_LC2_B2~NOT = LCELL( _EQ013);
_EQ013 = !q6
# !q5
# !_LC2_B7;
-- Node name is ':54'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ014);
_EQ014 = !q9
# !q8
# !q7
# !_LC2_B2;
Project Information g:\multiclock\count1024.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,220K
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