📄 clock.rpt
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_EQ002 = en & !_LC1_B2 & !_LC6_B2 & _LC7_B2
# !en & _LC1_B2;
-- Node name is '|CNT3:6|:8'
-- Equation name is '_LC7_B2', type is buried
_LC7_B2 = DFFE( _EQ003, _LC2_B2, GLOBAL(!clr), VCC, VCC);
_EQ003 = !en & _LC7_B2
# en & !_LC1_B2 & !_LC6_B2 & !_LC7_B2;
-- Node name is '|CNT4:5|:4'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = DFFE( _EQ004, _LC6_A1, GLOBAL(!clr), VCC, VCC);
_EQ004 = !en & _LC8_B2;
-- Node name is '|CNT4:5|:6'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = DFFE( _EQ005, _LC6_A1, GLOBAL(!clr), VCC, VCC);
_EQ005 = !en & _LC4_B2
# !_LC3_B2 & _LC4_B2 & !_LC8_B2
# en & _LC3_B2 & !_LC4_B2 & !_LC8_B2;
-- Node name is '|CNT4:5|:8'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = DFFE( _EQ006, _LC6_A1, GLOBAL(!clr), VCC, VCC);
_EQ006 = !en & _LC3_B2
# en & !_LC3_B2 & !_LC8_B2;
-- Node name is '|CNT4:5|:10'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = DFFE( _EQ007, _LC6_A1, VCC, VCC, VCC);
_EQ007 = _LC3_B2 & _LC4_B2 & !_LC8_B2;
-- Node name is '|CNT6:3|:4'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE( _EQ008, _LC1_A15, GLOBAL(!clr), VCC, VCC);
_EQ008 = en & _LC2_A1 & !_LC3_A1 & _LC4_A1
# !_LC2_A1 & _LC3_A1 & !_LC4_A1
# !en & _LC3_A1;
-- Node name is '|CNT6:3|:6'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = DFFE( _EQ009, _LC1_A15, GLOBAL(!clr), VCC, VCC);
_EQ009 = !en & _LC2_A1
# _LC2_A1 & !_LC3_A1 & !_LC4_A1
# en & !_LC2_A1 & !_LC3_A1 & _LC4_A1;
-- Node name is '|CNT6:3|:8'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = DFFE( _EQ010, _LC1_A15, GLOBAL(!clr), VCC, VCC);
_EQ010 = !en & _LC4_A1
# en & !_LC2_A1 & !_LC4_A1
# en & !_LC3_A1 & !_LC4_A1;
-- Node name is '|CNT6:3|:10'
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = DFFE( _EQ011, _LC1_A15, VCC, VCC, VCC);
_EQ011 = !_LC2_A1 & _LC3_A1 & _LC4_A1;
-- Node name is '|CNT6:4|:4'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = DFFE( _EQ012, _LC2_A19, GLOBAL(!clr), VCC, VCC);
_EQ012 = en & _LC1_A1 & _LC5_A1 & !_LC7_A1
# !_LC1_A1 & !_LC5_A1 & _LC7_A1
# !en & _LC7_A1;
-- Node name is '|CNT6:4|:6'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ013, _LC2_A19, GLOBAL(!clr), VCC, VCC);
_EQ013 = !en & _LC1_A1
# _LC1_A1 & !_LC5_A1 & !_LC7_A1
# en & !_LC1_A1 & _LC5_A1 & !_LC7_A1;
-- Node name is '|CNT6:4|:8'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = DFFE( _EQ014, _LC2_A19, GLOBAL(!clr), VCC, VCC);
_EQ014 = !en & _LC5_A1
# en & !_LC1_A1 & !_LC5_A1
# en & !_LC5_A1 & !_LC7_A1;
-- Node name is '|CNT6:4|:10'
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = DFFE( _EQ015, _LC2_A19, VCC, VCC, VCC);
_EQ015 = !_LC1_A1 & _LC5_A1 & _LC7_A1;
-- Node name is '|CNT10:1|LPM_ADD_SUB:78|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = LCELL( _EQ016);
_EQ016 = _LC3_A15 & _LC7_A15;
-- Node name is '|CNT10:1|LPM_ADD_SUB:78|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_A15', type is buried
_LC8_A15 = LCELL( _EQ017);
_EQ017 = !_LC3_A15 & _LC5_A15
# _LC5_A15 & !_LC7_A15
# !_LC2_A15 & _LC5_A15
# _LC2_A15 & _LC3_A15 & !_LC5_A15 & _LC7_A15;
-- Node name is '|CNT10:1|:4'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = DFFE( _EQ018, GLOBAL( clk1hz), GLOBAL(!clr), VCC, VCC);
_EQ018 = en & _LC4_A15 & _LC8_A15
# !en & _LC5_A15;
-- Node name is '|CNT10:1|:6'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = DFFE( _EQ019, GLOBAL( clk1hz), GLOBAL(!clr), VCC, VCC);
_EQ019 = _LC2_A15 & _LC4_A15 & !_LC6_A15
# en & !_LC2_A15 & _LC4_A15 & _LC6_A15
# !en & _LC2_A15;
-- Node name is '|CNT10:1|:8'
-- Equation name is '_LC3_A15', type is buried
_LC3_A15 = DFFE( _EQ020, GLOBAL( clk1hz), GLOBAL(!clr), VCC, VCC);
_EQ020 = _LC3_A15 & _LC4_A15 & !_LC7_A15
# en & !_LC3_A15 & _LC4_A15 & _LC7_A15
# !en & _LC3_A15;
-- Node name is '|CNT10:1|:10'
-- Equation name is '_LC7_A15', type is buried
_LC7_A15 = DFFE( _EQ021, GLOBAL( clk1hz), GLOBAL(!clr), VCC, VCC);
_EQ021 = en & _LC4_A15 & !_LC7_A15
# !en & _LC7_A15;
-- Node name is '|CNT10:1|:12'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = DFFE( _EQ022, GLOBAL( clk1hz), VCC, VCC, VCC);
_EQ022 = !_LC2_A15 & !_LC3_A15 & _LC5_A15 & _LC7_A15;
-- Node name is '|CNT10:1|:49'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = LCELL( _EQ023);
_EQ023 = !_LC5_A15
# !_LC2_A15 & !_LC3_A15 & !_LC7_A15;
-- Node name is '|CNT10:2|LPM_ADD_SUB:78|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A19', type is buried
_LC4_A19 = LCELL( _EQ024);
_EQ024 = _LC1_A19 & _LC8_A19;
-- Node name is '|CNT10:2|LPM_ADD_SUB:78|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_A19', type is buried
_LC7_A19 = LCELL( _EQ025);
_EQ025 = _LC6_A19 & !_LC8_A19
# !_LC1_A19 & _LC6_A19
# !_LC5_A19 & _LC6_A19
# _LC1_A19 & _LC5_A19 & !_LC6_A19 & _LC8_A19;
-- Node name is '|CNT10:2|:4'
-- Equation name is '_LC6_A19', type is buried
_LC6_A19 = DFFE( _EQ026, _LC8_A1, GLOBAL(!clr), VCC, VCC);
_EQ026 = en & _LC3_A19 & _LC7_A19
# !en & _LC6_A19;
-- Node name is '|CNT10:2|:6'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = DFFE( _EQ027, _LC8_A1, GLOBAL(!clr), VCC, VCC);
_EQ027 = _LC3_A19 & !_LC4_A19 & _LC5_A19
# en & _LC3_A19 & _LC4_A19 & !_LC5_A19
# !en & _LC5_A19;
-- Node name is '|CNT10:2|:8'
-- Equation name is '_LC8_A19', type is buried
_LC8_A19 = DFFE( _EQ028, _LC8_A1, GLOBAL(!clr), VCC, VCC);
_EQ028 = !_LC1_A19 & _LC3_A19 & _LC8_A19
# en & _LC1_A19 & _LC3_A19 & !_LC8_A19
# !en & _LC8_A19;
-- Node name is '|CNT10:2|:10'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = DFFE( _EQ029, _LC8_A1, GLOBAL(!clr), VCC, VCC);
_EQ029 = en & !_LC1_A19 & _LC3_A19
# !en & _LC1_A19;
-- Node name is '|CNT10:2|:12'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = DFFE( _EQ030, _LC8_A1, VCC, VCC, VCC);
_EQ030 = _LC1_A19 & !_LC5_A19 & _LC6_A19 & !_LC8_A19;
-- Node name is '|CNT10:2|:49'
-- Equation name is '_LC3_A19', type is buried
_LC3_A19 = LCELL( _EQ031);
_EQ031 = !_LC6_A19
# !_LC1_A19 & !_LC5_A19 & !_LC8_A19;
Project Informationc:\documents and settings\hjj\my documents\multiclock\clock.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 32,180K
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