📄 clock.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
61 - - B -- OUTPUT 0 1 0 0 hh0
64 - - B -- OUTPUT 0 1 0 0 hh1
62 - - B -- OUTPUT 0 1 0 0 hh2
50 - - - 02 OUTPUT 0 0 0 0 hh3
63 - - B -- OUTPUT 0 1 0 0 hl0
65 - - B -- OUTPUT 0 1 0 0 hl1
15 - - B -- OUTPUT 0 1 0 0 hl2
20 - - C -- OUTPUT 0 0 0 0 hl3
69 - - A -- OUTPUT 0 1 0 0 mh0
79 - - - 02 OUTPUT 0 1 0 0 mh1
68 - - A -- OUTPUT 0 1 0 0 mh2
45 - - - 11 OUTPUT 0 0 0 0 mh3
5 - - A -- OUTPUT 0 1 0 0 ml0
10 - - A -- OUTPUT 0 1 0 0 ml1
94 - - - 19 OUTPUT 0 1 0 0 ml2
29 - - - 19 OUTPUT 0 1 0 0 ml3
77 - - - 01 OUTPUT 0 1 0 0 sh0
78 - - - 01 OUTPUT 0 1 0 0 sh1
70 - - A -- OUTPUT 0 1 0 0 sh2
56 - - C -- OUTPUT 0 0 0 0 sh3
9 - - A -- OUTPUT 0 1 0 0 sl0
7 - - A -- OUTPUT 0 1 0 0 sl1
6 - - A -- OUTPUT 0 1 0 0 sl2
8 - - A -- OUTPUT 0 1 0 0 sl3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\clock.rpt
clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 02 DFFE 1 1 1 2 |CNT3:6|:4
- 1 - B 02 DFFE 1 3 1 1 |CNT3:6|:6
- 7 - B 02 DFFE 1 3 1 1 |CNT3:6|:8
- 8 - B 02 DFFE 1 1 1 3 |CNT4:5|:4
- 4 - B 02 DFFE 1 3 1 1 |CNT4:5|:6
- 3 - B 02 DFFE 1 2 1 2 |CNT4:5|:8
- 2 - B 02 DFFE 0 4 0 3 |CNT4:5|:10
- 3 - A 01 DFFE 1 3 1 3 |CNT6:3|:4
- 2 - A 01 DFFE 1 3 1 3 |CNT6:3|:6
- 4 - A 01 DFFE 1 3 1 3 |CNT6:3|:8
- 8 - A 01 DFFE 0 4 0 5 |CNT6:3|:10
- 7 - A 01 DFFE 1 3 1 3 |CNT6:4|:4
- 1 - A 01 DFFE 1 3 1 3 |CNT6:4|:6
- 5 - A 01 DFFE 1 3 1 3 |CNT6:4|:8
- 6 - A 01 DFFE 0 4 0 4 |CNT6:4|:10
- 6 - A 15 AND2 0 2 0 1 |CNT10:1|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - A 15 OR2 0 4 0 1 |CNT10:1|LPM_ADD_SUB:78|addcore:adder|:69
- 5 - A 15 DFFE + 1 2 1 3 |CNT10:1|:4
- 2 - A 15 DFFE + 1 2 1 3 |CNT10:1|:6
- 3 - A 15 DFFE + 1 2 1 4 |CNT10:1|:8
- 7 - A 15 DFFE + 1 1 1 5 |CNT10:1|:10
- 1 - A 15 DFFE + 0 4 0 4 |CNT10:1|:12
- 4 - A 15 OR2 0 4 0 4 |CNT10:1|:49
- 4 - A 19 AND2 0 2 0 1 |CNT10:2|LPM_ADD_SUB:78|addcore:adder|:55
- 7 - A 19 OR2 0 4 0 1 |CNT10:2|LPM_ADD_SUB:78|addcore:adder|:69
- 6 - A 19 DFFE 1 3 1 3 |CNT10:2|:4
- 5 - A 19 DFFE 1 3 1 3 |CNT10:2|:6
- 8 - A 19 DFFE 1 3 1 4 |CNT10:2|:8
- 1 - A 19 DFFE 1 2 1 5 |CNT10:2|:10
- 2 - A 19 DFFE 0 5 0 4 |CNT10:2|:12
- 3 - A 19 OR2 0 4 0 4 |CNT10:2|:49
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\clock.rpt
clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 2/ 48( 4%) 5/ 48( 10%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 2/ 96( 2%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\clock.rpt
clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk1hz
DFF 5 |CNT6:3|:10
DFF 4 |CNT6:4|:10
DFF 4 |CNT10:1|:12
DFF 4 |CNT10:2|:12
DFF 3 |CNT4:5|:10
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\clock.rpt
clock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 20 clr
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\clock.rpt
clock
** EQUATIONS **
clk1hz : INPUT;
clr : INPUT;
en : INPUT;
-- Node name is 'hh0'
-- Equation name is 'hh0', type is output
hh0 = _LC7_B2;
-- Node name is 'hh1'
-- Equation name is 'hh1', type is output
hh1 = _LC1_B2;
-- Node name is 'hh2'
-- Equation name is 'hh2', type is output
hh2 = _LC6_B2;
-- Node name is 'hh3'
-- Equation name is 'hh3', type is output
hh3 = GND;
-- Node name is 'hl0'
-- Equation name is 'hl0', type is output
hl0 = _LC3_B2;
-- Node name is 'hl1'
-- Equation name is 'hl1', type is output
hl1 = _LC4_B2;
-- Node name is 'hl2'
-- Equation name is 'hl2', type is output
hl2 = _LC8_B2;
-- Node name is 'hl3'
-- Equation name is 'hl3', type is output
hl3 = GND;
-- Node name is 'mh0'
-- Equation name is 'mh0', type is output
mh0 = _LC5_A1;
-- Node name is 'mh1'
-- Equation name is 'mh1', type is output
mh1 = _LC1_A1;
-- Node name is 'mh2'
-- Equation name is 'mh2', type is output
mh2 = _LC7_A1;
-- Node name is 'mh3'
-- Equation name is 'mh3', type is output
mh3 = GND;
-- Node name is 'ml0'
-- Equation name is 'ml0', type is output
ml0 = _LC1_A19;
-- Node name is 'ml1'
-- Equation name is 'ml1', type is output
ml1 = _LC8_A19;
-- Node name is 'ml2'
-- Equation name is 'ml2', type is output
ml2 = _LC5_A19;
-- Node name is 'ml3'
-- Equation name is 'ml3', type is output
ml3 = _LC6_A19;
-- Node name is 'sh0'
-- Equation name is 'sh0', type is output
sh0 = _LC4_A1;
-- Node name is 'sh1'
-- Equation name is 'sh1', type is output
sh1 = _LC2_A1;
-- Node name is 'sh2'
-- Equation name is 'sh2', type is output
sh2 = _LC3_A1;
-- Node name is 'sh3'
-- Equation name is 'sh3', type is output
sh3 = GND;
-- Node name is 'sl0'
-- Equation name is 'sl0', type is output
sl0 = _LC7_A15;
-- Node name is 'sl1'
-- Equation name is 'sl1', type is output
sl1 = _LC3_A15;
-- Node name is 'sl2'
-- Equation name is 'sl2', type is output
sl2 = _LC2_A15;
-- Node name is 'sl3'
-- Equation name is 'sl3', type is output
sl3 = _LC5_A15;
-- Node name is '|CNT3:6|:4'
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = DFFE( _EQ001, _LC2_B2, GLOBAL(!clr), VCC, VCC);
_EQ001 = !en & _LC6_B2;
-- Node name is '|CNT3:6|:6'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = DFFE( _EQ002, _LC2_B2, GLOBAL(!clr), VCC, VCC);
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