zdbs.vhd

来自「多功能时钟」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity zdbs is
port(clk,mc:in std_logic;
         bs:out std_logic);
end;
architecture one of zdbs is 
signal q:std_logic_vector(4 downto 0);
     begin
  q1:      process(mc,clk)
          begin
if mc='0' then q<="11111";
  elsif clk'event and clk='1' then 
    q<=q+1;
end if;

end process;
q2: process(q)
    begin 
        if q<10 then 
              bs<='1';
         else bs<='0';
     end if;
end process;
end;