📄 multiclock.rpt
字号:
multiclock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 13 DFFE + 0 1 0 2 |CNT3:38|:6
- 2 - B 13 DFFE + 0 1 0 2 |CNT3:38|:8
- 4 - B 13 DFFE + 0 2 0 1 |CNT3:38|:10
- 7 - F 05 DFFE 0 3 0 3 |CNT5:12|:4
- 6 - F 05 DFFE 0 3 0 2 |CNT5:12|:6
- 8 - F 05 DFFE 0 2 0 3 |CNT5:12|:8
- 2 - F 05 DFFE 0 4 0 2 |CNT5:12|:10
- 7 - B 07 DFFE + 0 3 0 4 |CNT10:9|:4
- 6 - B 07 DFFE + 0 3 0 3 |CNT10:9|:6
- 5 - B 07 DFFE + 0 2 0 4 |CNT10:9|:8
- 8 - B 07 DFFE + 0 3 0 4 |CNT10:9|:10
- 1 - B 07 DFFE + 0 4 0 5 |CNT10:9|:12
- 6 - B 11 DFFE 0 4 0 4 |CNT10:10|:4
- 4 - B 11 DFFE 0 4 0 3 |CNT10:10|:6
- 3 - B 11 DFFE 0 3 0 4 |CNT10:10|:8
- 7 - B 11 DFFE 0 4 0 4 |CNT10:10|:10
- 5 - B 11 DFFE 0 5 0 10 |CNT10:10|:12
- 3 - B 07 DFFE 0 4 0 4 |CNT10:11|:4
- 2 - B 07 DFFE 0 4 0 3 |CNT10:11|:6
- 2 - B 11 DFFE 0 3 0 4 |CNT10:11|:8
- 4 - B 07 DFFE 0 4 0 4 |CNT10:11|:10
- 1 - B 11 DFFE 0 5 0 9 |CNT10:11|:12
- 5 - F 24 OR2 1 2 1 0 |MUX4B:3|:24
- 5 - F 06 OR2 1 2 1 0 |MUX4B:3|:30
- 2 - F 24 OR2 1 2 1 0 |MUX4B:3|:36
- 1 - F 24 OR2 1 2 1 0 |MUX4B:3|:42
- 2 - F 22 AND2 1 1 1 0 |MUX4B:4|:25
- 1 - F 22 OR2 1 2 1 0 |MUX4B:4|:30
- 5 - F 23 OR2 1 2 1 0 |MUX4B:4|:36
- 2 - F 23 OR2 1 2 1 0 |MUX4B:4|:42
- 3 - F 07 OR2 1 2 1 0 |MUX4B:5|:24
- 6 - F 10 OR2 1 2 1 0 |MUX4B:5|:30
- 4 - F 20 OR2 1 2 1 0 |MUX4B:5|:36
- 7 - F 20 OR2 1 2 1 0 |MUX4B:5|:42
- 6 - F 06 OR2 1 2 1 0 |MUX4B:6|:30
- 3 - F 06 OR2 1 2 1 0 |MUX4B:6|:36
- 2 - F 07 OR2 1 2 1 0 |MUX4B:6|:42
- 2 - F 06 OR2 1 2 1 0 |MUX4B:7|:24
- 3 - F 10 OR2 1 2 1 0 |MUX4B:7|:30
- 7 - F 01 OR2 1 2 1 0 |MUX4B:7|:36
- 8 - F 02 OR2 1 2 1 0 |MUX4B:7|:42
- 5 - F 02 AND2 1 1 1 0 |MUX4B:8|:31
- 8 - F 10 OR2 1 2 1 0 |MUX4B:8|:36
- 1 - F 10 OR2 1 2 1 0 |MUX4B:8|:42
- 1 - F 19 OR2 s 2 2 0 1 |naoling:45|COMP8B:1|~53~1
- 3 - F 19 OR2 s 2 2 0 1 |naoling:45|COMP8B:1|~53~2
- 5 - F 19 OR2 s 2 1 0 1 |naoling:45|COMP8B:1|~53~3
- 7 - F 19 OR2 s 2 2 0 1 |naoling:45|COMP8B:1|~53~4
- 1 - B 22 OR2 ! 0 2 0 3 |naoling:45|COUNT1024:2|LPM_ADD_SUB:131|addcore:adder|:79
- 2 - B 17 OR2 ! 0 3 0 2 |naoling:45|COUNT1024:2|LPM_ADD_SUB:131|addcore:adder|:87
- 3 - B 17 OR2 ! 0 2 0 3 |naoling:45|COUNT1024:2|LPM_ADD_SUB:131|addcore:adder|:91
- 1 - B 17 OR2 ! 0 3 0 4 |naoling:45|COUNT1024:2|LPM_ADD_SUB:131|addcore:adder|:99
- 3 - B 22 DFFE + 0 3 0 2 |naoling:45|COUNT1024:2|q9 (|naoling:45|COUNT1024:2|:3)
- 7 - B 22 DFFE + 0 2 0 2 |naoling:45|COUNT1024:2|q8 (|naoling:45|COUNT1024:2|:4)
- 6 - B 22 DFFE + 0 2 0 3 |naoling:45|COUNT1024:2|q7 (|naoling:45|COUNT1024:2|:5)
- 7 - B 17 DFFE + 0 3 0 1 |naoling:45|COUNT1024:2|q6 (|naoling:45|COUNT1024:2|:6)
- 8 - B 17 DFFE + 0 2 0 2 |naoling:45|COUNT1024:2|q5 (|naoling:45|COUNT1024:2|:7)
- 6 - B 17 DFFE + 0 2 0 1 |naoling:45|COUNT1024:2|q4 (|naoling:45|COUNT1024:2|:8)
- 4 - B 17 DFFE + 0 3 0 1 |naoling:45|COUNT1024:2|q3 (|naoling:45|COUNT1024:2|:9)
- 5 - B 17 DFFE + 0 2 0 2 |naoling:45|COUNT1024:2|q2 (|naoling:45|COUNT1024:2|:10)
- 5 - B 22 DFFE + 0 2 0 1 |naoling:45|COUNT1024:2|q1 (|naoling:45|COUNT1024:2|:11)
- 4 - B 22 DFFE + 0 0 0 2 |naoling:45|COUNT1024:2|q0 (|naoling:45|COUNT1024:2|:12)
- 2 - B 22 OR2 0 4 0 7 |naoling:45|COUNT1024:2|:54
- 1 - B 13 OR2 1 3 1 0 |naoling:45|MUX1K500:3|:57
- 6 - F 19 DFFE + 0 4 0 1 |naoling:45|:11
- 2 - F 19 LCELL s 1 0 1 0 nl0~1
- 4 - F 19 LCELL s 1 0 1 0 nl1~1
- 8 - F 19 LCELL s 1 0 1 0 nl2~1
- 7 - C 23 LCELL s 1 0 1 0 nl3~1
- 5 - C 21 LCELL s 1 0 1 0 nl4~1
- 4 - C 18 LCELL s 1 0 1 0 nl5~1
- 7 - B 05 LCELL s 1 0 1 0 nl6~1
- 6 - B 09 LCELL s 1 0 1 0 nl7~1
- 4 - F 11 DFFE + 0 3 0 4 |paob:2|CNT10:12|:4
- 3 - F 11 DFFE + 0 3 0 3 |paob:2|CNT10:12|:6
- 2 - F 11 DFFE + 0 2 0 4 |paob:2|CNT10:12|:8
- 5 - F 11 DFFE + 0 3 0 4 |paob:2|CNT10:12|:10
- 1 - F 11 DFFE + 0 4 0 8 |paob:2|CNT10:12|:12
- 7 - F 02 DFFE 1 4 0 3 |paob:2|count:17|CNT6:27|:4
- 2 - F 02 DFFE 1 4 0 3 |paob:2|count:17|CNT6:27|:6
- 3 - F 02 DFFE 1 4 0 3 |paob:2|count:17|CNT6:27|:8
- 4 - F 07 DFFE 1 4 0 4 |paob:2|count:17|CNT6:28|:4
- 6 - F 07 DFFE 1 4 0 4 |paob:2|count:17|CNT6:28|:6
- 8 - F 07 DFFE 1 4 0 4 |paob:2|count:17|CNT6:28|:8
- 5 - F 07 DFFE 0 4 0 5 |paob:2|count:17|CNT6:28|:10
- 7 - F 18 AND2 0 2 0 1 |paob:2|count:17|CNT10:21|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - F 18 OR2 0 4 0 1 |paob:2|count:17|CNT10:21|LPM_ADD_SUB:78|addcore:adder|:69
- 1 - F 18 DFFE 1 4 0 4 |paob:2|count:17|CNT10:21|:4
- 2 - F 18 DFFE 1 4 0 4 |paob:2|count:17|CNT10:21|:6
- 5 - F 18 DFFE 1 4 0 5 |paob:2|count:17|CNT10:21|:8
- 3 - F 18 DFFE 1 3 0 6 |paob:2|count:17|CNT10:21|:10
- 4 - F 18 DFFE 0 5 0 5 |paob:2|count:17|CNT10:21|:12
- 6 - F 18 OR2 0 4 0 4 |paob:2|count:17|CNT10:21|:49
- 7 - F 15 AND2 0 2 0 1 |paob:2|count:17|CNT10:23|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - F 15 OR2 0 4 0 1 |paob:2|count:17|CNT10:23|LPM_ADD_SUB:78|addcore:adder|:69
- 3 - F 15 DFFE 1 4 0 4 |paob:2|count:17|CNT10:23|:4
- 4 - F 15 DFFE 1 4 0 4 |paob:2|count:17|CNT10:23|:6
- 1 - F 15 DFFE 1 4 0 5 |paob:2|count:17|CNT10:23|:8
- 2 - F 15 DFFE 1 3 0 6 |paob:2|count:17|CNT10:23|:10
- 5 - F 15 DFFE 0 5 0 5 |paob:2|count:17|CNT10:23|:12
- 6 - F 15 OR2 0 4 0 4 |paob:2|count:17|CNT10:23|:49
- 1 - F 07 AND2 0 2 0 1 |paob:2|count:17|CNT10:24|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - F 20 OR2 0 4 0 1 |paob:2|count:17|CNT10:24|LPM_ADD_SUB:78|addcore:adder|:69
- 3 - F 20 DFFE 1 4 0 4 |paob:2|count:17|CNT10:24|:4
- 5 - F 20 DFFE 1 4 0 4 |paob:2|count:17|CNT10:24|:6
- 1 - F 20 DFFE 1 4 0 5 |paob:2|count:17|CNT10:24|:8
- 2 - F 20 DFFE 1 3 0 6 |paob:2|count:17|CNT10:24|:10
- 7 - F 07 DFFE 0 5 0 4 |paob:2|count:17|CNT10:24|:12
- 6 - F 20 OR2 0 4 0 4 |paob:2|count:17|CNT10:24|:49
- 5 - F 08 AND2 0 2 0 1 |paob:2|count:17|CNT10:26|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - F 08 OR2 0 4 0 1 |paob:2|count:17|CNT10:26|LPM_ADD_SUB:78|addcore:adder|:69
- 6 - F 08 DFFE 1 4 0 4 |paob:2|count:17|CNT10:26|:4
- 7 - F 08 DFFE 1 4 0 4 |paob:2|count:17|CNT10:26|:6
- 4 - F 08 DFFE 1 4 0 5 |paob:2|count:17|CNT10:26|:8
- 2 - F 08 DFFE 1 3 0 6 |paob:2|count:17|CNT10:26|:10
- 1 - F 08 DFFE 0 5 0 3 |paob:2|count:17|CNT10:26|:12
- 3 - F 08 OR2 0 4 0 4 |paob:2|count:17|CNT10:26|:49
- 1 - F 02 DFFE 0 3 0 22 |paob:2|KEY:5|:3
- 6 - F 02 DFFE 1 2 0 1 |paob:2|KEY:5|state1 (|paob:2|KEY:5|:5)
- 4 - F 02 DFFE 1 1 0 2 |paob:2|KEY:5|state0 (|paob:2|KEY:5|:6)
- 7 - F 10 DFFE 0 3 0 3 |tsclock:43|CNT3:6|:6
- 5 - F 10 DFFE 0 3 0 2 |tsclock:43|CNT3:6|:8
- 3 - F 23 DFFE 1 3 0 4 |tsclock:43|CNT6:3|:4
- 7 - F 23 DFFE 1 3 0 4 |tsclock:43|CNT6:3|:6
- 6 - F 23 DFFE 1 3 0 4 |tsclock:43|CNT6:3|:8
- 4 - F 23 DFFE 0 4 0 1 |tsclock:43|CNT6:3|:10
- 1 - F 13 DFFE 1 3 0 5 |tsclock:43|CNT6:4|:4
- 2 - F 13 DFFE 1 3 0 5 |tsclock:43|CNT6:4|:6
- 3 - F 13 DFFE 1 3 0 5 |tsclock:43|CNT6:4|:8
- 1 - F 14 DFFE 0 4 0 6 |tsclock:43|CNT6:4|:10
- 7 - F 24 DFFE 1 4 0 5 |tsclock:43|CNT10:1|:4
- 6 - F 24 DFFE 1 4 0 4 |tsclock:43|CNT10:1|:6
- 4 - F 24 DFFE 1 3 0 5 |tsclock:43|CNT10:1|:8
- 3 - F 24 DFFE 1 4 0 5 |tsclock:43|CNT10:1|:10
- 8 - F 24 DFFE 0 5 0 4 |tsclock:43|CNT10:1|:12
- 4 - F 13 DFFE 1 4 0 6 |tsclock:43|CNT10:2|:4
- 6 - F 13 DFFE 1 4 0 5 |tsclock:43|CNT10:2|:6
- 5 - F 13 DFFE 1 3 0 6 |tsclock:43|CNT10:2|:8
- 7 - F 13 DFFE 1 4 0 6 |tsclock:43|CNT10:2|:10
- 8 - F 13 DFFE 0 5 0 4 |tsclock:43|CNT10:2|:12
- 1 - F 05 DFFE 0 5 0 5 |tsclock:43|CNT10:21|:4
- 4 - F 05 DFFE 0 5 0 5 |tsclock:43|CNT10:21|:6
- 3 - F 05 DFFE 0 4 0 5 |tsclock:43|CNT10:21|:8
- 5 - F 05 DFFE 0 5 0 5 |tsclock:43|CNT10:21|:10
- 4 - F 10 DFFE 0 5 0 2 |tsclock:43|CNT10:21|:12
- 1 - F 23 OR2 1 2 0 5 |tsclock:43|MUX21:26|:15
- 8 - F 23 OR2 1 2 0 5 |tsclock:43|MUX21:29|:15
- 2 - F 10 OR2 ! 0 2 0 6 |tsclock:43|:22
- 3 - F 14 AND2 0 2 0 3 |ZDBS:36|LPM_ADD_SUB:48|addcore:adder|:59
- 6 - F 14 DFFE ! 0 5 0 1 |ZDBS:36|q4 (|ZDBS:36|:4)
- 7 - F 14 DFFE ! 0 4 0 2 |ZDBS:36|q3 (|ZDBS:36|:5)
- 4 - F 14 DFFE ! 0 3 0 3 |ZDBS:36|q2 (|ZDBS:36|:6)
- 5 - F 14 DFFE ! 0 3 0 2 |ZDBS:36|q1 (|ZDBS:36|:7)
- 2 - F 14 DFFE ! 0 2 0 2 |ZDBS:36|q0 (|ZDBS:36|:8)
- 8 - F 14 OR2 0 4 1 0 |ZDBS:36|:89
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: g:\multiclock\multiclock.rpt
multiclock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 7/ 48( 14%) 5/ 48( 10%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
C: 6/ 96( 6%) 0/ 48( 0%) 3/ 48( 6%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
D: 7/ 96( 7%) 0/ 48( 0%) 0/ 48( 0%) 6/16( 37%) 1/16( 6%) 0/16( 0%)
E: 4/ 96( 4%) 2/ 48( 4%) 1/ 48( 2%) 3/16( 18%) 5/16( 31%) 0/16( 0%)
F: 28/ 96( 29%) 20/ 48( 41%) 27/ 48( 56%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\multiclock\multiclock.rpt
multiclock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 25 clkin
DFF 10 |CNT10:10|:12
DFF 9 |CNT10:11|:12
DFF 8 |paob:2|CNT10:12|:12
LCELL 5 |tsclock:43|MUX21:26|:15
DFF 5 |paob:2|count:17|CNT10:23|:12
DFF 5 |paob:2|count:17|CNT10:21|:12
DFF 5 |paob:2|count:17|CNT6:28|:10
DFF 5 |CNT10:9|:12
LCELL 5 |tsclock:43|MUX21:29|:15
DFF 4 |paob:2|count:17|CNT10:24|:12
DFF 4 |tsclock:43|CNT10:1|:12
DFF 4 |tsclock:43|CNT10:2|:12
DFF 3 |paob:2|count:17|CNT10:26|:12
DFF 2 |tsclock:43|CNT10:21|:12
Device-Specific Information: g:\multiclock\multiclock.rpt
multiclock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 36 clr
DFF 6 |tsclock:43|CNT6:4|:10
LCELL 6 |tsclock:43|:22
Device-Specific Information: g:\multiclock\multiclock.rpt
multiclock
** EQUATIONS **
clkin : INPUT;
clr : INPUT;
mode : INPUT;
nlsj0 : INPUT;
nlsj1 : INPUT;
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