📄 multiclock.rpt
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User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S G G G G V S S S S S S S S S S S S S
E E E E E G E E E E V E E E E G E N N N N C E E E E E E E V E E E E E E
R R R R R N R R R R C R R R R N R D D D D C R R R R R R R C R R R R R R
V V V V V D V V V V C V V V V D V I I I I I V V V V V V V C V V V V V V
E E E E E I E E E E I E E E E I E N N N N N E E E E E E E I E E E E E E
D D D D D O D D D D O D D D D O D T T T T T D D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | RESERVED
RESERVED | 9 100 | RESERVED
mode | 10 99 | speaker
RESERVED | 11 98 | RESERVED
clr | 12 97 | RESERVED
s_p | 13 96 | nl7
RESERVED | 14 95 | nl6
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
tm | 17 92 | nl5
th | 18 91 | nl4
RESERVED | 19 EPF10K20TC144-4 90 | nl3
nlsj0 | 20 89 | nl2
nlsj1 | 21 88 | nl1
nlsj2 | 22 87 | nl0
nlsj3 | 23 86 | ohh3
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
nlsj4 | 26 83 | ohh2
nlsj5 | 27 82 | ohh1
nlsj6 | 28 81 | ohh0
bs | 29 80 | ohl3
osl0 | 30 79 | ohl2
osl1 | 31 78 | ohl1
osl2 | 32 77 | ^MSEL0
osl3 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
osh0 | 36 73 | ohl0
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
o o o G o o R R V R R R R G R V V c G n G G R R V R R R o G o o o o V o
s s s N m m E E C E E E E N E C C l N l N N E E C E E E m N m m m m C m
h h h D l l S S C S S S S D S C C k D s D D S S C S S S l D l h h h C h
1 2 3 I 0 1 E E I E E E E I E I I i I j I I E E I E E E 2 I 3 0 1 2 I 3
O R R O R R R R O R N N n N 7 N N R R O R R R O O
V V V V V V V T T T T T V V V V V
E E E E E E E E E E E E
D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: g:\multiclock\multiclock.rpt
multiclock
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
B7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 1/22( 4%)
B9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
B11 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 4/22( 18%)
B13 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
B17 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B22 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 1/22( 4%)
C18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
F1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
F2 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 7/22( 31%)
F5 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 3/22( 13%)
F6 4/ 8( 50%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
F7 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 1/2 10/22( 45%)
F8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F10 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 11/22( 50%)
F11 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
F13 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 2/2 1/2 2/22( 9%)
F14 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 5/22( 22%)
F15 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F19 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 1/2 0/2 15/22( 68%)
F20 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
F22 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F23 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
F24 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 6/22( 27%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 46/96 ( 47%)
Total logic cells used: 155/1152 ( 13%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.18/4 ( 79%)
Total fan-in: 493/4608 ( 10%)
Total input pins required: 14
Total input I/O cell registers required: 0
Total output pins required: 34
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 155
Total flipflops required: 98
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 12/1152 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 1 0 8 0 1 0 7 0 0 4 0 0 0 8 0 0 0 0 7 0 0 36/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 3/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 1 8 0 0 8 4 8 8 0 8 5 0 0 8 8 8 0 0 8 8 8 0 2 8 8 116/0
Total: 1 8 0 0 9 4 16 8 1 8 12 0 0 12 8 8 0 8 9 8 8 1 9 9 8 155/0
Device-Specific Information: g:\multiclock\multiclock.rpt
multiclock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - -- INPUT G 0 0 0 1 clkin
12 - - C -- INPUT 0 0 0 36 clr
10 - - B -- INPUT 0 0 0 22 mode
20 - - D -- INPUT 0 0 0 2 nlsj0
21 - - D -- INPUT 0 0 0 2 nlsj1
22 - - D -- INPUT 0 0 0 2 nlsj2
23 - - D -- INPUT 0 0 0 2 nlsj3
26 - - E -- INPUT 0 0 0 2 nlsj4
27 - - E -- INPUT 0 0 0 2 nlsj5
28 - - E -- INPUT 0 0 0 2 nlsj6
56 - - - -- INPUT 0 0 0 2 nlsj7
13 - - C -- INPUT 0 0 0 2 s_p
18 - - D -- INPUT 0 0 0 1 th
17 - - D -- INPUT 0 0 0 1 tm
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: g:\multiclock\multiclock.rpt
multiclock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
29 - - E -- OUTPUT 0 1 0 0 bs
87 - - E -- OUTPUT 0 1 0 0 nl0
88 - - D -- OUTPUT 0 1 0 0 nl1
89 - - C -- OUTPUT 0 1 0 0 nl2
90 - - C -- OUTPUT 0 1 0 0 nl3
91 - - C -- OUTPUT 0 1 0 0 nl4
92 - - C -- OUTPUT 0 1 0 0 nl5
95 - - B -- OUTPUT 0 1 0 0 nl6
96 - - B -- OUTPUT 0 1 0 0 nl7
81 - - F -- OUTPUT 0 1 0 0 ohh0
82 - - E -- OUTPUT 0 1 0 0 ohh1
83 - - E -- OUTPUT 0 1 0 0 ohh2
86 - - E -- OUTPUT 0 0 0 0 ohh3
73 - - - 01 OUTPUT 0 1 0 0 ohl0
78 - - F -- OUTPUT 0 1 0 0 ohl1
79 - - F -- OUTPUT 0 1 0 0 ohl2
80 - - F -- OUTPUT 0 1 0 0 ohl3
68 - - - 07 OUTPUT 0 1 0 0 omh0
69 - - - 06 OUTPUT 0 1 0 0 omh1
70 - - - 05 OUTPUT 0 1 0 0 omh2
72 - - - 03 OUTPUT 0 0 0 0 omh3
41 - - - 20 OUTPUT 0 1 0 0 oml0
42 - - - 19 OUTPUT 0 1 0 0 oml1
65 - - - 09 OUTPUT 0 1 0 0 oml2
67 - - - 08 OUTPUT 0 1 0 0 oml3
36 - - - 24 OUTPUT 0 1 0 0 osh0
37 - - - 23 OUTPUT 0 1 0 0 osh1
38 - - - 22 OUTPUT 0 1 0 0 osh2
39 - - - 21 OUTPUT 0 1 0 0 osh3
30 - - F -- OUTPUT 0 1 0 0 osl0
31 - - F -- OUTPUT 0 1 0 0 osl1
32 - - F -- OUTPUT 0 1 0 0 osl2
33 - - F -- OUTPUT 0 1 0 0 osl3
99 - - B -- OUTPUT 0 1 0 0 speaker
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\multiclock\multiclock.rpt
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