multiclock.rpt

多功能时钟

Project Information                               g:\multiclock\multiclock.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/07/2006 22:55:25

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

multiclock
      EPF10K20TC144-4      14     34     0    0         0  %    155      13 %

User Pins:                 14     34     0  



Project Information                               g:\multiclock\multiclock.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Flipflop '|CNT3:38|:4' stuck at GND
Warning: Flipflop '|tsclock:43|CNT3:6|:4' stuck at GND


Project Information                               g:\multiclock\multiclock.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

multiclock@29                     bs
multiclock@54                     clkin
multiclock@12                     clr
multiclock@10                     mode
multiclock@20                     nlsj0
multiclock@21                     nlsj1
multiclock@22                     nlsj2
multiclock@23                     nlsj3
multiclock@26                     nlsj4
multiclock@27                     nlsj5
multiclock@28                     nlsj6
multiclock@87                     nl0
multiclock@88                     nl1
multiclock@89                     nl2
multiclock@90                     nl3
multiclock@91                     nl4
multiclock@92                     nl5
multiclock@95                     nl6
multiclock@96                     nl7
multiclock@81                     ohh0
multiclock@82                     ohh1
multiclock@83                     ohh2
multiclock@86                     ohh3
multiclock@73                     ohl0
multiclock@78                     ohl1
multiclock@79                     ohl2
multiclock@80                     ohl3
multiclock@68                     omh0
multiclock@69                     omh1
multiclock@70                     omh2
multiclock@72                     omh3
multiclock@41                     oml0
multiclock@42                     oml1
multiclock@65                     oml2
multiclock@67                     oml3
multiclock@36                     osh0
multiclock@37                     osh1
multiclock@38                     osh2
multiclock@39                     osh3
multiclock@30                     osl0
multiclock@31                     osl1
multiclock@32                     osl2
multiclock@33                     osl3
multiclock@13                     s_p
multiclock@99                     speaker
multiclock@18                     th
multiclock@17                     tm


Project Information                               g:\multiclock\multiclock.rpt

** FILE HIERARCHY **



|paob:2|
|paob:2|key:5|
|paob:2|cnt10:12|
|paob:2|cnt10:12|lpm_add_sub:78|
|paob:2|cnt10:12|lpm_add_sub:78|addcore:adder|
|paob:2|cnt10:12|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|paob:2|cnt10:12|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|paob:2|cnt10:12|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|paob:2|count:17|
|paob:2|count:17|cnt10:21|
|paob:2|count:17|cnt10:21|lpm_add_sub:78|
|paob:2|count:17|cnt10:21|lpm_add_sub:78|addcore:adder|
|paob:2|count:17|cnt10:21|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|paob:2|count:17|cnt10:21|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|paob:2|count:17|cnt10:21|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|paob:2|count:17|cnt10:26|
|paob:2|count:17|cnt10:26|lpm_add_sub:78|
|paob:2|count:17|cnt10:26|lpm_add_sub:78|addcore:adder|
|paob:2|count:17|cnt10:26|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|paob:2|count:17|cnt10:26|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|paob:2|count:17|cnt10:26|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|paob:2|count:17|cnt10:24|
|paob:2|count:17|cnt10:24|lpm_add_sub:78|
|paob:2|count:17|cnt10:24|lpm_add_sub:78|addcore:adder|
|paob:2|count:17|cnt10:24|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|paob:2|count:17|cnt10:24|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|paob:2|count:17|cnt10:24|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|paob:2|count:17|cnt10:23|
|paob:2|count:17|cnt10:23|lpm_add_sub:78|
|paob:2|count:17|cnt10:23|lpm_add_sub:78|addcore:adder|
|paob:2|count:17|cnt10:23|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|paob:2|count:17|cnt10:23|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|paob:2|count:17|cnt10:23|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|paob:2|count:17|cnt6:27|
|paob:2|count:17|cnt6:27|lpm_add_sub:61|
|paob:2|count:17|cnt6:27|lpm_add_sub:61|addcore:adder|
|paob:2|count:17|cnt6:27|lpm_add_sub:61|altshift:result_ext_latency_ffs|
|paob:2|count:17|cnt6:27|lpm_add_sub:61|altshift:carry_ext_latency_ffs|
|paob:2|count:17|cnt6:27|lpm_add_sub:61|altshift:oflow_ext_latency_ffs|
|paob:2|count:17|cnt6:28|
|paob:2|count:17|cnt6:28|lpm_add_sub:61|
|paob:2|count:17|cnt6:28|lpm_add_sub:61|addcore:adder|
|paob:2|count:17|cnt6:28|lpm_add_sub:61|altshift:result_ext_latency_ffs|
|paob:2|count:17|cnt6:28|lpm_add_sub:61|altshift:carry_ext_latency_ffs|
|paob:2|count:17|cnt6:28|lpm_add_sub:61|altshift:oflow_ext_latency_ffs|
|mux4b:3|
|mux4b:4|
|mux4b:6|
|mux4b:7|
|mux4b:8|
|mux4b:5|
|cnt10:9|
|cnt10:9|lpm_add_sub:78|
|cnt10:9|lpm_add_sub:78|addcore:adder|
|cnt10:9|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|cnt10:9|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|cnt10:9|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|cnt10:10|
|cnt10:10|lpm_add_sub:78|
|cnt10:10|lpm_add_sub:78|addcore:adder|
|cnt10:10|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|cnt10:10|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|cnt10:10|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|cnt10:11|
|cnt10:11|lpm_add_sub:78|
|cnt10:11|lpm_add_sub:78|addcore:adder|
|cnt10:11|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|cnt10:11|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|cnt10:11|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|cnt5:12|
|cnt5:12|lpm_add_sub:61|
|cnt5:12|lpm_add_sub:61|addcore:adder|
|cnt5:12|lpm_add_sub:61|altshift:result_ext_latency_ffs|
|cnt5:12|lpm_add_sub:61|altshift:carry_ext_latency_ffs|
|cnt5:12|lpm_add_sub:61|altshift:oflow_ext_latency_ffs|
|zdbs:36|
|zdbs:36|lpm_add_sub:48|
|zdbs:36|lpm_add_sub:48|addcore:adder|
|zdbs:36|lpm_add_sub:48|altshift:result_ext_latency_ffs|
|zdbs:36|lpm_add_sub:48|altshift:carry_ext_latency_ffs|
|zdbs:36|lpm_add_sub:48|altshift:oflow_ext_latency_ffs|
|cnt3:38|
|cnt3:38|lpm_add_sub:61|
|cnt3:38|lpm_add_sub:61|addcore:adder|
|cnt3:38|lpm_add_sub:61|altshift:result_ext_latency_ffs|
|cnt3:38|lpm_add_sub:61|altshift:carry_ext_latency_ffs|
|cnt3:38|lpm_add_sub:61|altshift:oflow_ext_latency_ffs|
|tsclock:43|
|tsclock:43|cnt10:1|
|tsclock:43|cnt10:1|lpm_add_sub:78|
|tsclock:43|cnt10:1|lpm_add_sub:78|addcore:adder|
|tsclock:43|cnt10:1|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|tsclock:43|cnt10:1|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|tsclock:43|cnt10:1|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|tsclock:43|cnt10:21|
|tsclock:43|cnt10:21|lpm_add_sub:78|
|tsclock:43|cnt10:21|lpm_add_sub:78|addcore:adder|
|tsclock:43|cnt10:21|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|tsclock:43|cnt10:21|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|tsclock:43|cnt10:21|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|tsclock:43|cnt10:2|
|tsclock:43|cnt10:2|lpm_add_sub:78|
|tsclock:43|cnt10:2|lpm_add_sub:78|addcore:adder|
|tsclock:43|cnt10:2|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|tsclock:43|cnt10:2|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|tsclock:43|cnt10:2|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|tsclock:43|cnt6:3|
|tsclock:43|cnt6:3|lpm_add_sub:61|
|tsclock:43|cnt6:3|lpm_add_sub:61|addcore:adder|
|tsclock:43|cnt6:3|lpm_add_sub:61|altshift:result_ext_latency_ffs|
|tsclock:43|cnt6:3|lpm_add_sub:61|altshift:carry_ext_latency_ffs|
|tsclock:43|cnt6:3|lpm_add_sub:61|altshift:oflow_ext_latency_ffs|
|tsclock:43|cnt6:4|
|tsclock:43|cnt6:4|lpm_add_sub:61|
|tsclock:43|cnt6:4|lpm_add_sub:61|addcore:adder|
|tsclock:43|cnt6:4|lpm_add_sub:61|altshift:result_ext_latency_ffs|
|tsclock:43|cnt6:4|lpm_add_sub:61|altshift:carry_ext_latency_ffs|
|tsclock:43|cnt6:4|lpm_add_sub:61|altshift:oflow_ext_latency_ffs|
|tsclock:43|cnt3:6|
|tsclock:43|cnt3:6|lpm_add_sub:61|
|tsclock:43|cnt3:6|lpm_add_sub:61|addcore:adder|
|tsclock:43|cnt3:6|lpm_add_sub:61|altshift:result_ext_latency_ffs|
|tsclock:43|cnt3:6|lpm_add_sub:61|altshift:carry_ext_latency_ffs|
|tsclock:43|cnt3:6|lpm_add_sub:61|altshift:oflow_ext_latency_ffs|
|tsclock:43|mux21:26|
|tsclock:43|mux21:29|
|naoling:45|
|naoling:45|comp8b:1|
|naoling:45|count1024:2|
|naoling:45|count1024:2|lpm_add_sub:131|
|naoling:45|count1024:2|lpm_add_sub:131|addcore:adder|
|naoling:45|count1024:2|lpm_add_sub:131|altshift:result_ext_latency_ffs|
|naoling:45|count1024:2|lpm_add_sub:131|altshift:carry_ext_latency_ffs|
|naoling:45|count1024:2|lpm_add_sub:131|altshift:oflow_ext_latency_ffs|
|naoling:45|mux1k500:3|


Device-Specific Information:                      g:\multiclock\multiclock.rpt
multiclock

***** Logic for device 'multiclock' compiled without errors.




Device: EPF10K20TC144-4

FLEX 10K Configuration Scheme: Passive Serial

Device Options: