mux4b.vhd

来自「多功能时钟」· VHDL 代码 · 共 13 行

library ieee;
use ieee.std_logic_1164.all;
entity mux4b is
      port(in1,in2:in std_logic_vector(3 downto 0);
           sel:in std_logic;
           y:out std_logic_vector(3 downto 0));
end;
architecture one of mux4b is
begin
     y<=in1 when sel='1' else
        in2;
end;