mux21.vhd

来自「多功能时钟」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_1164.all;
entity mux21 is
      port(in1,in2:in std_logic;
           sel:in std_logic;
           y:out std_logic);
end;
architecture one of mux21 is
begin
     y<=in1 when sel='1' else
        in2;
end;