📄 paob.rpt
字号:
# _LC1_F23 & _LC3_F22 & !_LC6_F22 & _LC7_F23;
-- Node name is '|count:17|CNT10:23|:4'
-- Equation name is '_LC6_F22', type is buried
_LC6_F22 = DFFE( _EQ023, _LC4_F23, !clr, VCC, VCC);
_EQ023 = _LC1_F19 & _LC2_F23 & _LC7_F22
# !_LC2_F23 & _LC6_F22;
-- Node name is '|count:17|CNT10:23|:6'
-- Equation name is '_LC3_F22', type is buried
_LC3_F22 = DFFE( _EQ024, _LC4_F23, !clr, VCC, VCC);
_EQ024 = _LC1_F19 & _LC3_F22 & !_LC4_F22
# _LC1_F19 & _LC2_F23 & !_LC3_F22 & _LC4_F22
# !_LC2_F23 & _LC3_F22;
-- Node name is '|count:17|CNT10:23|:8'
-- Equation name is '_LC1_F23', type is buried
_LC1_F23 = DFFE( _EQ025, _LC4_F23, !clr, VCC, VCC);
_EQ025 = _LC1_F19 & _LC1_F23 & !_LC7_F23
# _LC1_F19 & !_LC1_F23 & _LC2_F23 & _LC7_F23
# _LC1_F23 & !_LC2_F23;
-- Node name is '|count:17|CNT10:23|:10'
-- Equation name is '_LC7_F23', type is buried
_LC7_F23 = DFFE( _EQ026, _LC4_F23, !clr, VCC, VCC);
_EQ026 = _LC1_F19 & _LC2_F23 & !_LC7_F23
# !_LC2_F23 & _LC7_F23;
-- Node name is '|count:17|CNT10:23|:12'
-- Equation name is '_LC3_F19', type is buried
_LC3_F19 = DFFE( _EQ027, _LC4_F23, VCC, VCC, VCC);
_EQ027 = !_LC1_F23 & !_LC3_F22 & _LC6_F22 & _LC7_F23;
-- Node name is '|count:17|CNT10:23|:49'
-- Equation name is '_LC1_F19', type is buried
_LC1_F19 = LCELL( _EQ028);
_EQ028 = !_LC6_F22
# !_LC1_F23 & !_LC3_F22 & !_LC7_F23;
-- Node name is '|count:17|CNT10:24|LPM_ADD_SUB:78|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_F19', type is buried
_LC8_F19 = LCELL( _EQ029);
_EQ029 = _LC5_F19 & _LC6_F19;
-- Node name is '|count:17|CNT10:24|LPM_ADD_SUB:78|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_F19', type is buried
_LC4_F19 = LCELL( _EQ030);
_EQ030 = _LC1_F8 & !_LC5_F19
# _LC1_F8 & !_LC6_F19
# _LC1_F8 & !_LC2_F9
# !_LC1_F8 & _LC2_F9 & _LC5_F19 & _LC6_F19;
-- Node name is '|count:17|CNT10:24|:4'
-- Equation name is '_LC1_F8', type is buried
_LC1_F8 = DFFE( _EQ031, _LC3_F19, !clr, VCC, VCC);
_EQ031 = _LC2_F23 & _LC4_F19 & _LC7_F19
# _LC1_F8 & !_LC2_F23;
-- Node name is '|count:17|CNT10:24|:6'
-- Equation name is '_LC2_F9', type is buried
_LC2_F9 = DFFE( _EQ032, _LC3_F19, !clr, VCC, VCC);
_EQ032 = _LC2_F9 & _LC7_F19 & !_LC8_F19
# !_LC2_F9 & _LC2_F23 & _LC7_F19 & _LC8_F19
# _LC2_F9 & !_LC2_F23;
-- Node name is '|count:17|CNT10:24|:8'
-- Equation name is '_LC5_F19', type is buried
_LC5_F19 = DFFE( _EQ033, _LC3_F19, !clr, VCC, VCC);
_EQ033 = _LC5_F19 & !_LC6_F19 & _LC7_F19
# _LC2_F23 & !_LC5_F19 & _LC6_F19 & _LC7_F19
# !_LC2_F23 & _LC5_F19;
-- Node name is '|count:17|CNT10:24|:10'
-- Equation name is '_LC6_F19', type is buried
_LC6_F19 = DFFE( _EQ034, _LC3_F19, !clr, VCC, VCC);
_EQ034 = _LC2_F23 & !_LC6_F19 & _LC7_F19
# !_LC2_F23 & _LC6_F19;
-- Node name is '|count:17|CNT10:24|:12'
-- Equation name is '_LC2_F19', type is buried
_LC2_F19 = DFFE( _EQ035, _LC3_F19, VCC, VCC, VCC);
_EQ035 = _LC1_F8 & !_LC2_F9 & !_LC5_F19 & _LC6_F19;
-- Node name is '|count:17|CNT10:24|:49'
-- Equation name is '_LC7_F19', type is buried
_LC7_F19 = LCELL( _EQ036);
_EQ036 = !_LC1_F8
# !_LC2_F9 & !_LC5_F19 & !_LC6_F19;
-- Node name is '|count:17|CNT10:26|LPM_ADD_SUB:78|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_F1', type is buried
_LC6_F1 = LCELL( _EQ037);
_EQ037 = _LC3_F1 & _LC7_F1;
-- Node name is '|count:17|CNT10:26|LPM_ADD_SUB:78|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_F1', type is buried
_LC8_F1 = LCELL( _EQ038);
_EQ038 = _LC2_F1 & !_LC7_F1
# _LC2_F1 & !_LC3_F1
# _LC2_F1 & !_LC4_F1
# !_LC2_F1 & _LC3_F1 & _LC4_F1 & _LC7_F1;
-- Node name is '|count:17|CNT10:26|:4'
-- Equation name is '_LC2_F1', type is buried
_LC2_F1 = DFFE( _EQ039, _LC2_F5, !clr, VCC, VCC);
_EQ039 = _LC2_F23 & _LC5_F1 & _LC8_F1
# _LC2_F1 & !_LC2_F23;
-- Node name is '|count:17|CNT10:26|:6'
-- Equation name is '_LC4_F1', type is buried
_LC4_F1 = DFFE( _EQ040, _LC2_F5, !clr, VCC, VCC);
_EQ040 = _LC4_F1 & _LC5_F1 & !_LC6_F1
# _LC2_F23 & !_LC4_F1 & _LC5_F1 & _LC6_F1
# !_LC2_F23 & _LC4_F1;
-- Node name is '|count:17|CNT10:26|:8'
-- Equation name is '_LC7_F1', type is buried
_LC7_F1 = DFFE( _EQ041, _LC2_F5, !clr, VCC, VCC);
_EQ041 = !_LC3_F1 & _LC5_F1 & _LC7_F1
# _LC2_F23 & _LC3_F1 & _LC5_F1 & !_LC7_F1
# !_LC2_F23 & _LC7_F1;
-- Node name is '|count:17|CNT10:26|:10'
-- Equation name is '_LC3_F1', type is buried
_LC3_F1 = DFFE( _EQ042, _LC2_F5, !clr, VCC, VCC);
_EQ042 = _LC2_F23 & !_LC3_F1 & _LC5_F1
# !_LC2_F23 & _LC3_F1;
-- Node name is '|count:17|CNT10:26|:12'
-- Equation name is '_LC1_F1', type is buried
_LC1_F1 = DFFE( _EQ043, _LC2_F5, VCC, VCC, VCC);
_EQ043 = _LC2_F1 & _LC3_F1 & !_LC4_F1 & !_LC7_F1;
-- Node name is '|count:17|CNT10:26|:49'
-- Equation name is '_LC5_F1', type is buried
_LC5_F1 = LCELL( _EQ044);
_EQ044 = !_LC2_F1
# !_LC3_F1 & !_LC4_F1 & !_LC7_F1;
-- Node name is '|KEY:5|:6' = '|KEY:5|state0'
-- Equation name is '_LC1_F21', type is buried
_LC1_F21 = DFFE(!s_p, _LC6_F21, VCC, VCC, VCC);
-- Node name is '|KEY:5|:5' = '|KEY:5|state1'
-- Equation name is '_LC5_F23', type is buried
_LC5_F23 = DFFE( _EQ045, _LC6_F21, VCC, VCC, VCC);
_EQ045 = !_LC1_F21 & _LC5_F23
# _LC5_F23 & !s_p
# _LC1_F21 & !_LC5_F23 & s_p;
-- Node name is '|KEY:5|:3'
-- Equation name is '_LC2_F23', type is buried
_LC2_F23 = DFFE( _EQ046, _LC6_F21, VCC, VCC, VCC);
_EQ046 = !_LC1_F21 & _LC5_F23
# _LC1_F21 & !_LC5_F23;
Project Information d:\hjj\multiclock\paob.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,710K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -