📄 paob.rpt
字号:
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 27/96 ( 28%)
Total logic cells used: 47/1152 ( 4%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.57/4 ( 89%)
Total fan-in: 168/4608 ( 3%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 25
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 47
Total flipflops required: 35
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/1152 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 8 0 0 0 3 0 0 2 4 0 0 0 0 0 0 0 0 0 0 8 0 6 8 8 0 47/0
Total: 8 0 0 0 3 0 0 2 4 0 0 0 0 0 0 0 0 0 0 8 0 6 8 8 0 47/0
Device-Specific Information: d:\hjj\multiclock\paob.rpt
paob
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
56 - - - -- INPUT G 0 0 0 0 clk
10 - - B -- INPUT 0 0 0 22 clr
12 - - C -- INPUT 0 0 0 2 s_p
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\hjj\multiclock\paob.rpt
paob
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
138 - - - 21 OUTPUT 0 1 0 0 clk10ms
81 - - F -- OUTPUT 0 1 0 0 mh0
82 - - E -- OUTPUT 0 1 0 0 mh1
83 - - E -- OUTPUT 0 1 0 0 mh2
17 - - D -- OUTPUT 0 0 0 0 mh3
73 - - - 01 OUTPUT 0 1 0 0 ml0
78 - - F -- OUTPUT 0 1 0 0 ml1
79 - - F -- OUTPUT 0 1 0 0 ml2
80 - - F -- OUTPUT 0 1 0 0 ml3
36 - - - 24 OUTPUT 0 1 0 0 msh0
37 - - - 23 OUTPUT 0 1 0 0 msh1
38 - - - 22 OUTPUT 0 1 0 0 msh2
39 - - - 21 OUTPUT 0 1 0 0 msh3
30 - - F -- OUTPUT 0 1 0 0 msl0
31 - - F -- OUTPUT 0 1 0 0 msl1
32 - - F -- OUTPUT 0 1 0 0 msl2
33 - - F -- OUTPUT 0 1 0 0 msl3
68 - - - 07 OUTPUT 0 1 0 0 sh0
69 - - - 06 OUTPUT 0 1 0 0 sh1
70 - - - 05 OUTPUT 0 1 0 0 sh2
119 - - - 07 OUTPUT 0 0 0 0 sh3
41 - - - 20 OUTPUT 0 1 0 0 sl0
42 - - - 19 OUTPUT 0 1 0 0 sl1
65 - - - 09 OUTPUT 0 1 0 0 sl2
67 - - - 08 OUTPUT 0 1 0 0 sl3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\hjj\multiclock\paob.rpt
paob
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - F 21 DFFE + 0 3 0 4 |CNT10:12|:4
- 3 - F 21 DFFE + 0 3 0 3 |CNT10:12|:6
- 2 - F 21 DFFE + 0 2 0 4 |CNT10:12|:8
- 5 - F 21 DFFE + 0 3 0 4 |CNT10:12|:10
- 6 - F 21 DFFE + 0 4 1 8 |CNT10:12|:12
- 6 - F 09 DFFE 1 4 1 2 |count:17|CNT6:27|:4
- 8 - F 09 DFFE 1 4 1 2 |count:17|CNT6:27|:6
- 1 - F 09 DFFE 1 4 1 2 |count:17|CNT6:27|:8
- 1 - F 05 DFFE 1 4 1 3 |count:17|CNT6:28|:4
- 4 - F 05 DFFE 1 4 1 3 |count:17|CNT6:28|:6
- 2 - F 08 DFFE 1 4 1 3 |count:17|CNT6:28|:8
- 2 - F 05 DFFE 0 4 0 5 |count:17|CNT6:28|:10
- 8 - F 22 AND2 0 2 0 1 |count:17|CNT10:21|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - F 23 OR2 0 4 0 1 |count:17|CNT10:21|LPM_ADD_SUB:78|addcore:adder|:69
- 6 - F 23 DFFE 1 4 1 3 |count:17|CNT10:21|:4
- 5 - F 22 DFFE 1 4 1 3 |count:17|CNT10:21|:6
- 2 - F 22 DFFE 1 4 1 4 |count:17|CNT10:21|:8
- 1 - F 22 DFFE 1 3 1 5 |count:17|CNT10:21|:10
- 4 - F 23 DFFE 0 5 0 5 |count:17|CNT10:21|:12
- 3 - F 23 OR2 0 4 0 4 |count:17|CNT10:21|:49
- 4 - F 22 AND2 0 2 0 1 |count:17|CNT10:23|LPM_ADD_SUB:78|addcore:adder|:55
- 7 - F 22 OR2 0 4 0 1 |count:17|CNT10:23|LPM_ADD_SUB:78|addcore:adder|:69
- 6 - F 22 DFFE 1 4 1 3 |count:17|CNT10:23|:4
- 3 - F 22 DFFE 1 4 1 3 |count:17|CNT10:23|:6
- 1 - F 23 DFFE 1 4 1 4 |count:17|CNT10:23|:8
- 7 - F 23 DFFE 1 3 1 5 |count:17|CNT10:23|:10
- 3 - F 19 DFFE 0 5 0 5 |count:17|CNT10:23|:12
- 1 - F 19 OR2 0 4 0 4 |count:17|CNT10:23|:49
- 8 - F 19 AND2 0 2 0 1 |count:17|CNT10:24|LPM_ADD_SUB:78|addcore:adder|:55
- 4 - F 19 OR2 0 4 0 1 |count:17|CNT10:24|LPM_ADD_SUB:78|addcore:adder|:69
- 1 - F 08 DFFE 1 4 1 3 |count:17|CNT10:24|:4
- 2 - F 09 DFFE 1 4 1 3 |count:17|CNT10:24|:6
- 5 - F 19 DFFE 1 4 1 4 |count:17|CNT10:24|:8
- 6 - F 19 DFFE 1 3 1 5 |count:17|CNT10:24|:10
- 2 - F 19 DFFE 0 5 0 4 |count:17|CNT10:24|:12
- 7 - F 19 OR2 0 4 0 4 |count:17|CNT10:24|:49
- 6 - F 01 AND2 0 2 0 1 |count:17|CNT10:26|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - F 01 OR2 0 4 0 1 |count:17|CNT10:26|LPM_ADD_SUB:78|addcore:adder|:69
- 2 - F 01 DFFE 1 4 1 3 |count:17|CNT10:26|:4
- 4 - F 01 DFFE 1 4 1 3 |count:17|CNT10:26|:6
- 7 - F 01 DFFE 1 4 1 4 |count:17|CNT10:26|:8
- 3 - F 01 DFFE 1 3 1 5 |count:17|CNT10:26|:10
- 1 - F 01 DFFE 0 5 0 3 |count:17|CNT10:26|:12
- 5 - F 01 OR2 0 4 0 4 |count:17|CNT10:26|:49
- 2 - F 23 DFFE 0 3 0 22 |KEY:5|:3
- 5 - F 23 DFFE 1 2 0 1 |KEY:5|state1 (|KEY:5|:5)
- 1 - F 21 DFFE 1 1 0 2 |KEY:5|state0 (|KEY:5|:6)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\hjj\multiclock\paob.rpt
paob
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
E: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
F: 9/ 96( 9%) 9/ 48( 18%) 14/ 48( 29%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\hjj\multiclock\paob.rpt
paob
** CLOCK SIGNALS **
Type Fan-out Name
DFF 9 |CNT10:12|:12
INPUT 5 clk
DFF 5 |count:17|CNT6:28|:10
DFF 5 |count:17|CNT10:21|:12
DFF 5 |count:17|CNT10:23|:12
DFF 4 |count:17|CNT10:24|:12
DFF 3 |count:17|CNT10:26|:12
Device-Specific Information: d:\hjj\multiclock\paob.rpt
paob
** CLEAR SIGNALS **
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