mux1k500.vhd

来自「多功能时钟」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
entity mux1k500 is
      port(clk1k,clk500,en:in std_logic;
           sel:in std_logic;
          y:out std_logic);
end;
architecture one of mux1k500 is
begin
process(en,sel)
begin
    if en='0' then y<='0';
    elsif en='1' then  
      if sel='1' then  y<=clk1k;
         else y<=clk500;
end if ;
end if ;
end process;
end;