comp8b.vhd

来自「多功能时钟」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comp8b is
port(a,b:in std_logic_vector(7 downto 0);
     
     c:out std_logic);
end;
architecture one of comp8b is 
  begin
process(a,b)
begin
if a=b then c<='1';
else c<='0';
end if;
end process;
end;