📄 count.rpt
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-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = DFFE( _EQ001, _LC7_B6, GLOBAL(!clr), VCC, VCC);
_EQ001 = _LC2_B6 & !_LC3_B6 & _LC6_B6
# !_LC2_B6 & _LC3_B6 & !_LC6_B6;
-- Node name is '|CNT6:4|:6'
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = DFFE( _EQ002, _LC7_B6, GLOBAL(!clr), VCC, VCC);
_EQ002 = !_LC2_B6 & !_LC3_B6 & _LC6_B6
# _LC2_B6 & !_LC3_B6 & !_LC6_B6;
-- Node name is '|CNT6:4|:8'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = DFFE( _EQ003, _LC7_B6, GLOBAL(!clr), VCC, VCC);
_EQ003 = !_LC2_B6 & !_LC6_B6
# !_LC2_B6 & !_LC3_B6;
-- Node name is '|CNT6:6|:4'
-- Equation name is '_LC4_A22', type is buried
_LC4_A22 = DFFE( _EQ004, _LC5_A22, GLOBAL(!clr), VCC, VCC);
_EQ004 = _LC2_A22 & !_LC4_A22 & _LC7_A22
# !_LC2_A22 & _LC4_A22 & !_LC7_A22;
-- Node name is '|CNT6:6|:6'
-- Equation name is '_LC7_A22', type is buried
_LC7_A22 = DFFE( _EQ005, _LC5_A22, GLOBAL(!clr), VCC, VCC);
_EQ005 = !_LC2_A22 & !_LC4_A22 & _LC7_A22
# _LC2_A22 & !_LC4_A22 & !_LC7_A22;
-- Node name is '|CNT6:6|:8'
-- Equation name is '_LC2_A22', type is buried
_LC2_A22 = DFFE( _EQ006, _LC5_A22, GLOBAL(!clr), VCC, VCC);
_EQ006 = !_LC2_A22 & !_LC7_A22
# !_LC2_A22 & !_LC4_A22;
-- Node name is '|CNT10:1|:4'
-- Equation name is '_LC2_C24', type is buried
_LC2_C24 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ007 = _LC1_C24 & !_LC2_C24 & _LC5_C24 & _LC6_C24
# !_LC1_C24 & _LC2_C24 & !_LC5_C24 & !_LC6_C24;
-- Node name is '|CNT10:1|:6'
-- Equation name is '_LC6_C24', type is buried
_LC6_C24 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ008 = !_LC1_C24 & !_LC2_C24 & _LC6_C24
# !_LC2_C24 & !_LC5_C24 & _LC6_C24
# _LC1_C24 & !_LC2_C24 & _LC5_C24 & !_LC6_C24;
-- Node name is '|CNT10:1|:8'
-- Equation name is '_LC1_C24', type is buried
_LC1_C24 = DFFE( _EQ009, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ009 = _LC1_C24 & !_LC2_C24 & !_LC5_C24
# !_LC1_C24 & !_LC2_C24 & _LC5_C24;
-- Node name is '|CNT10:1|:10'
-- Equation name is '_LC5_C24', type is buried
_LC5_C24 = DFFE( _EQ010, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ010 = !_LC1_C24 & !_LC5_C24 & !_LC6_C24
# !_LC2_C24 & !_LC5_C24;
-- Node name is '|CNT10:1|:185'
-- Equation name is '_LC3_C24', type is buried
_LC3_C24 = LCELL( _EQ011);
_EQ011 = !_LC1_C24 & _LC2_C24 & _LC5_C24 & !_LC6_C24;
-- Node name is '|CNT10:2|:4'
-- Equation name is '_LC3_B16', type is buried
_LC3_B16 = DFFE( _EQ012, _LC3_C24, GLOBAL(!clr), VCC, VCC);
_EQ012 = _LC1_B16 & !_LC3_B16 & _LC5_B16 & _LC8_B16
# !_LC1_B16 & _LC3_B16 & !_LC5_B16 & !_LC8_B16;
-- Node name is '|CNT10:2|:6'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = DFFE( _EQ013, _LC3_C24, GLOBAL(!clr), VCC, VCC);
_EQ013 = _LC1_B16 & !_LC3_B16 & !_LC8_B16
# _LC1_B16 & !_LC3_B16 & !_LC5_B16
# !_LC1_B16 & !_LC3_B16 & _LC5_B16 & _LC8_B16;
-- Node name is '|CNT10:2|:8'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = DFFE( _EQ014, _LC3_C24, GLOBAL(!clr), VCC, VCC);
_EQ014 = !_LC3_B16 & !_LC5_B16 & _LC8_B16
# !_LC3_B16 & _LC5_B16 & !_LC8_B16;
-- Node name is '|CNT10:2|:10'
-- Equation name is '_LC5_B16', type is buried
_LC5_B16 = DFFE( _EQ015, _LC3_C24, GLOBAL(!clr), VCC, VCC);
_EQ015 = !_LC1_B16 & !_LC5_B16 & !_LC8_B16
# !_LC3_B16 & !_LC5_B16;
-- Node name is '|CNT10:2|~50~1'
-- Equation name is '_LC2_B16', type is buried
-- synthesized logic cell
_LC2_B16 = LCELL( _EQ016);
_EQ016 = !_LC1_B16 & !_LC8_B16;
-- Node name is '|CNT10:3|:4'
-- Equation name is '_LC4_B6', type is buried
_LC4_B6 = DFFE( _EQ017, _LC4_B16, GLOBAL(!clr), VCC, VCC);
_EQ017 = _LC1_B6 & !_LC4_B6 & _LC7_B16 & _LC8_B6
# !_LC1_B6 & _LC4_B6 & !_LC7_B16 & !_LC8_B6;
-- Node name is '|CNT10:3|:6'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = DFFE( _EQ018, _LC4_B16, GLOBAL(!clr), VCC, VCC);
_EQ018 = _LC1_B6 & !_LC4_B6 & !_LC7_B16
# _LC1_B6 & !_LC4_B6 & !_LC8_B6
# !_LC1_B6 & !_LC4_B6 & _LC7_B16 & _LC8_B6;
-- Node name is '|CNT10:3|:8'
-- Equation name is '_LC7_B16', type is buried
_LC7_B16 = DFFE( _EQ019, _LC4_B16, GLOBAL(!clr), VCC, VCC);
_EQ019 = !_LC4_B6 & _LC7_B16 & !_LC8_B6
# !_LC4_B6 & !_LC7_B16 & _LC8_B6;
-- Node name is '|CNT10:3|:10'
-- Equation name is '_LC8_B6', type is buried
_LC8_B6 = DFFE( _EQ020, _LC4_B16, GLOBAL(!clr), VCC, VCC);
_EQ020 = !_LC1_B6 & !_LC7_B16 & !_LC8_B6
# !_LC4_B6 & !_LC8_B6;
-- Node name is '|CNT10:3|:185'
-- Equation name is '_LC7_B6', type is buried
_LC7_B6 = LCELL( _EQ021);
_EQ021 = !_LC1_B6 & _LC4_B6 & !_LC7_B16 & _LC8_B6;
-- Node name is '|CNT10:7|:4'
-- Equation name is '_LC8_A22', type is buried
_LC8_A22 = DFFE( _EQ022, _LC5_B6, GLOBAL(!clr), VCC, VCC);
_EQ022 = _LC1_A22 & _LC3_A22 & _LC6_A22 & !_LC8_A22
# !_LC1_A22 & !_LC3_A22 & !_LC6_A22 & _LC8_A22;
-- Node name is '|CNT10:7|:6'
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = DFFE( _EQ023, _LC5_B6, GLOBAL(!clr), VCC, VCC);
_EQ023 = !_LC3_A22 & _LC6_A22 & !_LC8_A22
# !_LC1_A22 & _LC6_A22 & !_LC8_A22
# _LC1_A22 & _LC3_A22 & !_LC6_A22 & !_LC8_A22;
-- Node name is '|CNT10:7|:8'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = DFFE( _EQ024, _LC5_B6, GLOBAL(!clr), VCC, VCC);
_EQ024 = !_LC1_A22 & _LC3_A22 & !_LC8_A22
# _LC1_A22 & !_LC3_A22 & !_LC8_A22;
-- Node name is '|CNT10:7|:10'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = DFFE( _EQ025, _LC5_B6, GLOBAL(!clr), VCC, VCC);
_EQ025 = !_LC1_A22 & !_LC3_A22 & !_LC6_A22
# !_LC1_A22 & !_LC8_A22;
-- Node name is '|CNT10:7|:185'
-- Equation name is '_LC5_A22', type is buried
_LC5_A22 = LCELL( _EQ026);
_EQ026 = _LC1_A22 & !_LC3_A22 & !_LC6_A22 & _LC8_A22;
-- Node name is ':19'
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = LCELL( _EQ027);
_EQ027 = _LC2_B16 & _LC3_B16 & _LC3_C24 & _LC5_B16;
-- Node name is ':20'
-- Equation name is '_LC5_B6', type is buried
_LC5_B6 = LCELL( _EQ028);
_EQ028 = _LC2_B6 & _LC3_B6 & !_LC6_B6 & _LC7_B6;
Project Informationc:\documents and settings\hjj\my documents\multiclock\count.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,585K
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