📄 count.rpt
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Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\count.rpt
count
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
72 - - A -- OUTPUT 0 1 0 0 mh0
69 - - A -- OUTPUT 0 1 0 0 mh1
81 - - - 22 OUTPUT 0 1 0 0 mh2
16 - - A -- OUTPUT 0 1 0 0 ml0
71 - - A -- OUTPUT 0 1 0 0 ml1
19 - - A -- OUTPUT 0 1 0 0 ml2
70 - - A -- OUTPUT 0 1 0 0 ml3
49 - - - 16 OUTPUT 0 1 0 0 msh0
65 - - B -- OUTPUT 0 1 0 0 msh1
67 - - B -- OUTPUT 0 1 0 0 msh2
66 - - B -- OUTPUT 0 1 0 0 msh3
59 - - C -- OUTPUT 0 1 0 0 msl0
62 - - C -- OUTPUT 0 1 0 0 msl1
58 - - C -- OUTPUT 0 1 0 0 msl2
61 - - C -- OUTPUT 0 1 0 0 msl3
17 - - A -- OUTPUT 0 1 0 0 sh0
24 - - B -- OUTPUT 0 1 0 0 sh1
23 - - B -- OUTPUT 0 1 0 0 sh2
25 - - B -- OUTPUT 0 1 0 0 sl0
64 - - B -- OUTPUT 0 1 0 0 sl1
22 - - B -- OUTPUT 0 1 0 0 sl2
21 - - B -- OUTPUT 0 1 0 0 sl3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\count.rpt
count
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 06 DFFE 0 3 1 3 |CNT6:4|:4
- 6 - B 06 DFFE 0 3 1 3 |CNT6:4|:6
- 2 - B 06 DFFE 0 3 1 3 |CNT6:4|:8
- 4 - A 22 DFFE 0 3 1 2 |CNT6:6|:4
- 7 - A 22 DFFE 0 3 1 2 |CNT6:6|:6
- 2 - A 22 DFFE 0 3 1 2 |CNT6:6|:8
- 2 - C 24 DFFE + 0 3 1 4 |CNT10:1|:4
- 6 - C 24 DFFE + 0 3 1 3 |CNT10:1|:6
- 1 - C 24 DFFE + 0 2 1 4 |CNT10:1|:8
- 5 - C 24 DFFE + 0 3 1 4 |CNT10:1|:10
- 3 - C 24 AND2 0 4 0 5 |CNT10:1|:185
- 3 - B 16 DFFE 0 4 1 4 |CNT10:2|:4
- 1 - B 16 DFFE 0 4 1 3 |CNT10:2|:6
- 8 - B 16 DFFE 0 3 1 4 |CNT10:2|:8
- 5 - B 16 DFFE 0 4 1 4 |CNT10:2|:10
- 2 - B 16 AND2 s 0 2 0 1 |CNT10:2|~50~1
- 4 - B 06 DFFE 0 4 1 4 |CNT10:3|:4
- 1 - B 06 DFFE 0 4 1 3 |CNT10:3|:6
- 7 - B 16 DFFE 0 3 1 4 |CNT10:3|:8
- 8 - B 06 DFFE 0 4 1 4 |CNT10:3|:10
- 7 - B 06 AND2 0 4 0 4 |CNT10:3|:185
- 8 - A 22 DFFE 0 4 1 4 |CNT10:7|:4
- 6 - A 22 DFFE 0 4 1 3 |CNT10:7|:6
- 3 - A 22 DFFE 0 3 1 4 |CNT10:7|:8
- 1 - A 22 DFFE 0 4 1 4 |CNT10:7|:10
- 5 - A 22 AND2 0 4 0 3 |CNT10:7|:185
- 4 - B 16 AND2 0 4 0 4 :19
- 5 - B 06 AND2 0 4 0 4 :20
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\count.rpt
count
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 1/ 48( 2%) 4/ 48( 8%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 4/ 96( 4%) 5/ 48( 10%) 5/ 48( 10%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\count.rpt
count
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 5 |CNT10:1|:185
INPUT 4 clk
LCELL 4 |CNT10:3|:185
LCELL 4 :19
LCELL 4 :20
LCELL 3 |CNT10:7|:185
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\count.rpt
count
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 22 clr
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\count.rpt
count
** EQUATIONS **
clk : INPUT;
clr : INPUT;
-- Node name is 'mh0'
-- Equation name is 'mh0', type is output
mh0 = _LC2_A22;
-- Node name is 'mh1'
-- Equation name is 'mh1', type is output
mh1 = _LC7_A22;
-- Node name is 'mh2'
-- Equation name is 'mh2', type is output
mh2 = _LC4_A22;
-- Node name is 'ml0'
-- Equation name is 'ml0', type is output
ml0 = _LC1_A22;
-- Node name is 'ml1'
-- Equation name is 'ml1', type is output
ml1 = _LC3_A22;
-- Node name is 'ml2'
-- Equation name is 'ml2', type is output
ml2 = _LC6_A22;
-- Node name is 'ml3'
-- Equation name is 'ml3', type is output
ml3 = _LC8_A22;
-- Node name is 'msh0'
-- Equation name is 'msh0', type is output
msh0 = _LC5_B16;
-- Node name is 'msh1'
-- Equation name is 'msh1', type is output
msh1 = _LC8_B16;
-- Node name is 'msh2'
-- Equation name is 'msh2', type is output
msh2 = _LC1_B16;
-- Node name is 'msh3'
-- Equation name is 'msh3', type is output
msh3 = _LC3_B16;
-- Node name is 'msl0'
-- Equation name is 'msl0', type is output
msl0 = _LC5_C24;
-- Node name is 'msl1'
-- Equation name is 'msl1', type is output
msl1 = _LC1_C24;
-- Node name is 'msl2'
-- Equation name is 'msl2', type is output
msl2 = _LC6_C24;
-- Node name is 'msl3'
-- Equation name is 'msl3', type is output
msl3 = _LC2_C24;
-- Node name is 'sh0'
-- Equation name is 'sh0', type is output
sh0 = _LC2_B6;
-- Node name is 'sh1'
-- Equation name is 'sh1', type is output
sh1 = _LC6_B6;
-- Node name is 'sh2'
-- Equation name is 'sh2', type is output
sh2 = _LC3_B6;
-- Node name is 'sl0'
-- Equation name is 'sl0', type is output
sl0 = _LC8_B6;
-- Node name is 'sl1'
-- Equation name is 'sl1', type is output
sl1 = _LC7_B16;
-- Node name is 'sl2'
-- Equation name is 'sl2', type is output
sl2 = _LC1_B6;
-- Node name is 'sl3'
-- Equation name is 'sl3', type is output
sl3 = _LC4_B6;
-- Node name is '|CNT6:4|:4'
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