📄 cnt10.rpt
字号:
- 6 - A 01 AND2 0 2 0 1 |LPM_ADD_SUB:78|addcore:adder|:55
- 8 - A 01 OR2 0 4 0 1 |LPM_ADD_SUB:78|addcore:adder|:69
- 7 - A 01 DFFE + 1 2 1 3 :4
- 2 - A 01 DFFE + 1 2 1 3 :6
- 5 - A 01 DFFE + 1 2 1 4 :8
- 1 - A 01 DFFE + 1 1 1 5 :10
- 3 - A 01 DFFE + 0 4 1 0 :12
- 4 - A 01 OR2 0 4 0 4 :49
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\cnt10.rpt
cnt10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\cnt10.rpt
cnt10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\cnt10.rpt
cnt10
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clr
Device-Specific Information:c:\documents and settings\hjj\my documents\multiclock\cnt10.rpt
cnt10
** EQUATIONS **
clk : INPUT;
clr : INPUT;
en : INPUT;
-- Node name is 'c10'
-- Equation name is 'c10', type is output
c10 = _LC3_A1;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC1_A1;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC5_A1;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC2_A1;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC7_A1;
-- Node name is '|LPM_ADD_SUB:78|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ001);
_EQ001 = _LC1_A1 & _LC5_A1;
-- Node name is '|LPM_ADD_SUB:78|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ002);
_EQ002 = !_LC5_A1 & _LC7_A1
# !_LC1_A1 & _LC7_A1
# !_LC2_A1 & _LC7_A1
# _LC1_A1 & _LC2_A1 & _LC5_A1 & !_LC7_A1;
-- Node name is ':4'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = en & _LC4_A1 & _LC8_A1
# !en & _LC7_A1;
-- Node name is ':6'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = _LC2_A1 & _LC4_A1 & !_LC6_A1
# en & !_LC2_A1 & _LC4_A1 & _LC6_A1
# !en & _LC2_A1;
-- Node name is ':8'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ005 = !_LC1_A1 & _LC4_A1 & _LC5_A1
# en & _LC1_A1 & _LC4_A1 & !_LC5_A1
# !en & _LC5_A1;
-- Node name is ':10'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ006 = en & !_LC1_A1 & _LC4_A1
# !en & _LC1_A1;
-- Node name is ':12'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC1_A1 & !_LC2_A1 & !_LC5_A1 & _LC7_A1;
-- Node name is ':49'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ008);
_EQ008 = !_LC7_A1
# !_LC1_A1 & !_LC2_A1 & !_LC5_A1;
Project Informationc:\documents and settings\hjj\my documents\multiclock\cnt10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 22,611K
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