clps9312.h

这是Skyeye 0.9 版本的源代码

#define SECURITY_OFFSET         0x030000
#define SECURITY_BASE           (EP93XX_APB_BASE|SECURITY_OFFSET)
#define SECFLG                  (SECURITY_BASE+0x2400)
#define SECEN                   (SECURITY_BASE+0x2410)
#define UNIQID                  (SECURITY_BASE+0x2440)
#define UNIQCHK                 (SECURITY_BASE+0x2450)
#define UNIQVAL                 (SECURITY_BASE+0x2460)
#define CLINBOOT                (SECURITY_BASE+0x2480)
#define CLINVADDR               (SECURITY_BASE+0x2484)
#define CLSETSKRNL              (SECURITY_BASE+0x2488)
#define CLSKRNL                 (SECURITY_BASE+0x248C)
#define ITTMP                   (SECURITY_BASE+0x2490)
#define ETBL1                   (SECURITY_BASE+0x24A0)
#define ETCL1                   (SECURITY_BASE+0x24A4)
#define ETAPL1                  (SECURITY_BASE+0x24A8)
#define ETSPTREG1               (SECURITY_BASE+0x24B0)
#define ETSPTREG2               (SECURITY_BASE+0x24B4)
#define ETSPTREG3               (SECURITY_BASE+0x24B8)
  
#define SECID1                  (SECURITY_BASE+0x2500)
#define SECID2                  (SECURITY_BASE+0x2504)
#define SECCHK1                 (SECURITY_BASE+0x2520)
#define SECCHK2                 (SECURITY_BASE+0x2524)
#define SECVAL1                 (SECURITY_BASE+0x2540)
#define SECVAL2                 (SECURITY_BASE+0x2544)
  
#define UNIQID2                 (SECURITY_BASE+0x2700)
#define UNIQID3                 (SECURITY_BASE+0x2704)
#define UNIQID4                 (SECURITY_BASE+0x2708)
#define UNIQID5                 (SECURITY_BASE+0x270C)
#define UNIQCHK2                (SECURITY_BASE+0x2710)
#define USRFLG                  (SECURITY_BASE+0x2714)
#define UNIQVAL2                (SECURITY_BASE+0x2720)
#define UNIQVAL3                (SECURITY_BASE+0x2724)
#define UNIQVAL4                (SECURITY_BASE+0x2728)
#define TESTVAL                 (SECURITY_BASE+0x2744)
#define TESTCHK                 (SECURITY_BASE+0x2754)
#define ACHK1                   (SECURITY_BASE+0x27A0)
#define ACHK2                   (SECURITY_BASE+0x27A4)
#define PROCRESET               (SECURITY_BASE+0x27A8)
#define TESTIDR                 (SECURITY_BASE+0x27AC)
#define AVAL1                   (SECURITY_BASE+0x27B0)
#define AVAL2                   (SECURITY_BASE+0x27B4)
#define AID1                    (SECURITY_BASE+0x27C4)
#define AID2                    (SECURITY_BASE+0x27C8)
#define ADYNREMAP               (SECURITY_BASE+0x27D0)
#define ALTTMP                  (SECURITY_BASE+0x27D4)
#define PROCSIGN                (SECURITY_BASE+0x27F0)
  
#define ECLIDX                  (SECURITY_BASE+0x2800)
#define ECLINE0                 (SECURITY_BASE+0x2810)
#define ECLINE1                 (SECURITY_BASE+0x2814)
#define ECLINE2                 (SECURITY_BASE+0x2818)
#define ECLINE3                 (SECURITY_BASE+0x281C)
#define ECLINE4                 (SECURITY_BASE+0x2820)
#define ECLINE5                 (SECURITY_BASE+0x2824)
#define ECLINE6                 (SECURITY_BASE+0x2828)
#define ECLINE7                 (SECURITY_BASE+0x282C)
#define ETWIDX1                 (SECURITY_BASE+0x2840)
#define ETWL1                   (SECURITY_BASE+0x2844)
#define ETWIDX2                 (SECURITY_BASE+0x2848)
#define ETWL2                   (SECURITY_BASE+0x284C)
  
#define ETSPT10                 (SECURITY_BASE+0x4000)
#define ETSPT11                 (SECURITY_BASE+0x4004)
#define ETSPT12                 (SECURITY_BASE+0x4008)
#define ETSPT13                 (SECURITY_BASE+0x400C)
  
#define ETSPT2000               (SECURITY_BASE+0x6000)
#define ETSPT2020               (SECURITY_BASE+0x6020)
#define ETSPT2024               (SECURITY_BASE+0x6024)
  
/* 8084_0000 - 8084_ffff: GPIO */ 
#define GPIO_OFFSET              0x040000
#define GPIO_BASE                (EP93XX_APB_BASE|GPIO_OFFSET)
#define GPIO_PADR                HW_REG(GPIO_BASE+0x00)
#define GPIO_PBDR                HW_REG(GPIO_BASE+0x04)
#define GPIO_PCDR                HW_REG(GPIO_BASE+0x08)
#define GPIO_PDDR                HW_REG(GPIO_BASE+0x0C)
#define GPIO_PADDR               HW_REG(GPIO_BASE+0x10)
#define GPIO_PBDDR               HW_REG(GPIO_BASE+0x14)
#define GPIO_PCDDR               HW_REG(GPIO_BASE+0x18)
#define GPIO_PDDDR               HW_REG(GPIO_BASE+0x1C)
#define GPIO_PEDR                HW_REG(GPIO_BASE+0x20)
#define GPIO_PEDDR               HW_REG(GPIO_BASE+0x24)
// #define 0x8084.0028 Reserved
// #define 0x8084.002C Reserved
#define GPIO_PFDR                HW_REG(GPIO_BASE+0x30) 
#define GPIO_PFDDR               HW_REG(GPIO_BASE+0x34)
#define GPIO_PGDR                HW_REG(GPIO_BASE+0x38)
#define GPIO_PGDDR               HW_REG(GPIO_BASE+0x3C)
#define GPIO_PHDR                HW_REG(GPIO_BASE+0x40)
#define GPIO_PHDDR               HW_REG(GPIO_BASE+0x44)
// #define 0x8084.0048 RAZ RAZ                                  
#define GPIO_INTTYPE1            HW_REG(GPIO_BASE+0x4C)
#define GPIO_INTTYPE2            HW_REG(GPIO_BASE+0x50)
#define GPIO_FEOI                HW_REG(GPIO_BASE+0x54) /* WRITE ONLY - READ UNDEFINED */
#define GPIO_INTEN               HW_REG(GPIO_BASE+0x58)
#define GPIO_INTSTATUS           HW_REG(GPIO_BASE+0x5C)
#define GPIO_RAWINTSTASUS        HW_REG(GPIO_BASE+0x60) 
#define GPIO_FDB                 HW_REG(GPIO_BASE+0x64)
#define GPIO_PAPINDR             HW_REG(GPIO_BASE+0x68)
#define GPIO_PBPINDR             HW_REG(GPIO_BASE+0x6C)
#define GPIO_PCPINDR             HW_REG(GPIO_BASE+0x70)
#define GPIO_PDPINDR             HW_REG(GPIO_BASE+0x74)
#define GPIO_PEPINDR             HW_REG(GPIO_BASE+0x78)
#define GPIO_PFPINDR             HW_REG(GPIO_BASE+0x7C)
#define GPIO_PGPINDR             HW_REG(GPIO_BASE+0x80)
#define GPIO_PHPINDR             HW_REG(GPIO_BASE+0x84)
#define GPIO_AINTTYPE1           HW_REG(GPIO_BASE+0x90) /*                           */
#define GPIO_AINTTYPE2           HW_REG(GPIO_BASE+0x94) /*                            */
#define GPIO_AEOI                HW_REG(GPIO_BASE+0x98) /* WRITE ONLY - READ UNDEFINED */
#define GPIO_AINTEN              HW_REG(GPIO_BASE+0x9C) /*                         */
#define GPIO_INTSTATUSA          HW_REG(GPIO_BASE+0xA0) /* */
#define GPIO_RAWINTSTSTISA       HW_REG(GPIO_BASE+0xA4) /* */
#define GPIO_ADB                 HW_REG(GPIO_BASE+0xA8) /*              */
#define GPIO_BINTTYPE1           HW_REG(GPIO_BASE+0xAC) /*                      */
#define GPIO_BINTTYPE2           HW_REG(GPIO_BASE+0xB0) /*                         */
#define GPIO_BEOI                HW_REG(GPIO_BASE+0xB4) /* WRITE ONLY - READ UNDEFINED */
#define GPIO_BINTEN              HW_REG(GPIO_BASE+0xB8) /*                         */
#define GPIO_INTSTATUSB          HW_REG(GPIO_BASE+0xBC) /* */
#define GPIO_RAWINTSTSTISB       HW_REG(GPIO_BASE+0xC0) /* */
#define GPIO_BDB                 HW_REG(GPIO_BASE+0xC4) /*              */
#define GPIO_EEDRIVE             HW_REG(GPIO_BASE+0xC8) /* */
//#define Reserved               (GPIO_BASE+0xCC)
#define GPIO_TCR                 HW_REG(GPIO_BASE+0xD0) /* Test Registers */
#define GPIO_TISRA               HW_REG(GPIO_BASE+0xD4) /* Test Registers */
#define GPIO_TISRB               HW_REG(GPIO_BASE+0xD8) /* Test Registers */
#define GPIO_TISRC               HW_REG(GPIO_BASE+0xDC) /* Test Registers */
#define GPIO_TISRD               HW_REG(GPIO_BASE+0xE0) /* Test Registers */
#define GPIO_TISRE               HW_REG(GPIO_BASE+0xE4) /* Test Registers */
#define GPIO_TISRF               HW_REG(GPIO_BASE+0xE8) /* Test Registers */
#define GPIO_TISRG               HW_REG(GPIO_BASE+0xEC) /* Test Registers */
#define GPIO_TISRH               HW_REG(GPIO_BASE+0xF0) /* Test Registers */
#define GPIO_TCER                HW_REG(GPIO_BASE+0xF4) /* Test Registers */
  
/* 8085_0000 - 8085_ffff: Reserved  */ 
  
/* 8086_0000 - 8086_ffff: Reserved  */ 
  
/* 8087_0000 - 8087_ffff: Reserved  */ 
  
/* 8088_0000 - 8088_ffff: Ac97 Controller (AAC) */ 
#define AAC_OFFSET             0x080000
#define AAC_BASE               (EP93XX_APB_BASE|AAC_OFFSET)
#define AACDR1                 (AAC_BASE+0x00) /* 8088.0000 R/W Data read or written from/to FIFO1  */
#define AACRXCR1               (AAC_BASE+0x04) /* 8088.0004 R/W Control register for receive        */
#define AACTXCR1               (AAC_BASE+0x08) /* 8088.0008 R/W Control register for transmit       */
#define AACSR1                 (AAC_BASE+0x0C) /* 8088.000C R   Status register                     */
#define AACRISR1               (AAC_BASE+0x10) /* 8088.0010 R   Raw interrupt status register       */
#define AACISR1                (AAC_BASE+0x14) /* 8088.0014 R   Interrupt Status                    */
#define AACIE1                 (AAC_BASE+0x18) /* 8088.0018 R/W Interrupt Enable                    */
  /* 8088.001C Reserved - RAZ                          */ 
#define AACDR2                 (AAC_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2  */
#define AACRXCR2               (AAC_BASE+0x24) /* 8088.0024 R/W Control register for receive        */
#define AACTXCR2               (AAC_BASE+0x28) /* 8088.0028 R/W Control register for transmit       */
#define AACSR2                 (AAC_BASE+0x2C) /* 8088.002C R   Status register                     */
#define AACRISR2               (AAC_BASE+0x30) /* 8088.0030 R   Raw interrupt status register       */
#define AACISR2                (AAC_BASE+0x34) /* 8088.0034 R   Interrupt Status                    */
#define AACIE2                 (AAC_BASE+0x38) /* 8088.0038 R/W Interrupt Enable                    */
  /* 8088.003C Reserved - RAZ                          */ 
#define AACDR3                 (AAC_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */
#define AACRXCR3               (AAC_BASE+0x44) /* 8088.0044 R/W Control register for receive        */
#define AACTXCR3               (AAC_BASE+0x48) /* 8088.0048 R/W Control register for transmit       */
#define AACSR3                 (AAC_BASE+0x4C) /* 8088.004C R   Status register                     */
#define AACRISR3               (AAC_BASE+0x50) /* 8088.0050 R   Raw interrupt status register       */
#define AACISR3                (AAC_BASE+0x54) /* 8088.0054 R   Interrupt Status                    */
#define AACIE3                 (AAC_BASE+0x58) /* 8088.0058 R/W Interrupt Enable                    */
  /* 8088.005C Reserved - RAZ                          */ 
#define AACDR4                 (AAC_BASE+0x60) /* 8088.0060 R/W Data read or written from/to FIFO4. */
#define AACRXCR4               (AAC_BASE+0x64) /* 8088.0064 R/W Control register for receive        */
#define AACTXCR4               (AAC_BASE+0x68) /* 8088.0068 R/W Control register for transmit       */
#define AACSR4                 (AAC_BASE+0x6C) /* 8088.006C R   Status register                     */
#define AACRISR4               (AAC_BASE+0x70) /* 8088.0070 R   Raw interrupt status register       */
#define AACISR4                (AAC_BASE+0x74) /* 8088.0074 R   Interrupt Status                    */
#define AACIE4                 (AAC_BASE+0x78) /* 8088.0078 R/W Interrupt Enable                    */
  /* 8088.007C Reserved - RAZ                          */ 
#define AACS1DATA              (AAC_BASE+0x80) /* 8088.0080 R/W Data received/transmitted on SLOT1  */
#define AACS2DATA              (AAC_BASE+0x84) /* 8088.0084 R/W Data received/transmitted on SLOT2  */
#define AACS12DATA             (AAC_BASE+0x88) /* 8088.0088 R/W Data received/transmitted on SLOT12 */
#define AACRGIS                (AAC_BASE+0x8C) /* 8088.008C R/W Raw Global interrupt status register*/
#define AACGIS                 (AAC_BASE+0x90) /* 8088.0090 R   Global interrupt status register    */
#define AACIM                  (AAC_BASE+0x94) /* 8088.0094 R/W Interrupt mask register             */
#define AACEOI                 (AAC_BASE+0x98) /* 8088.0098 W   Interrupt clear register            */
#define AACGCR                 (AAC_BASE+0x9C) /* 8088.009C R/W Main Control register               */
#define AACRESET               (AAC_BASE+0xA0) /* 8088.00A0 R/W RESET control register.             */
#define AACSYNC                (AAC_BASE+0xA4) /* 8088.00A4 R/W SYNC control register.              */
#define AACGCIS                (AAC_BASE+0xA8) /* 8088.00A8 R  Global chan FIFO int status register */
  
/* 8089_0000 - 8089_ffff: Reserved */ 
  
/* 808A_0000 - 808A_ffff: SSP - (SPI) */ 
#define SSP_OFFSET             0x0A0000
#define SSP_BASE               (EP93XX_APB_BASE|SSP_OFFSET)
///#define SSPCR0                 HW_REG(SSP_BASE+0x00) /* 0x808A.0000 R/W Control register 0                */
///#define SSPCR1                 HW_REG(SSP_BASE+0x04) /* 0x808A.0004 R/W Control register 1.               */
///#define SSPIIR                 HW_REG(SSP_BASE+0x08) /* 0x808A.0008 R   Interrupt ID register             */
///#define SSPICR                 HW_REG(SSP_BASE+0x08) /* 0x808A.0008 W   Interrupt clear register          */
///#define SSPDR                  HW_REG(SSP_BASE+0x0C) /* 0x808A.000C R/W  Receive FIFO (Read)              */
///                                                     /*                  Transmit FIFO  (Write)           */
///#define SSPCPSR                HW_REG(SSP_BASE+0x10) /* 0x808A.0010 R/W Clock prescale register           */
///#define SSPSR                  HW_REG(SSP_BASE+0x14) /* 0x808A.0014 R   Status register                   */
  
/*808B_0000 - 808B_ffff: IrDA */ 
#define IRDA_OFFSET             0x0B0000
#define IRDA_BASE               (E