📄 xscale_copro.c
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mmu_cache_exit (MAIN_D_CACHE ());
mmu_tlb_exit (D_TLB ());
mmu_cache_exit (I_CACHE ());
mmu_tlb_exit (I_TLB ());
};
static fault_t
xscale_mmu_load_instr (ARMul_State * state, ARMword va, ARMword * instr)
{
fault_t fault;
tlb_entry_t *tlb;
cache_line_t *cache;
int c; //cache bit
ARMword pa; //physical addr
static int debug_count = 0; //used for debug
d_msg ("va = %x\n", va);
va = mmu_pid_va_map (va);
if (MMU_Enabled)
{
/*align check */
if ((va & (WORD_SIZE - 1)) && MMU_Aligned)
{
d_msg ("align\n");
return ALIGNMENT_FAULT;
}
else
va &= ~(WORD_SIZE - 1);
/*translate tlb */
fault = translate (state, va, I_TLB (), &tlb);
if (fault)
{
d_msg ("translate\n");
return fault;
}
/*check access */
fault = check_access (state, va, tlb, 1);
if (fault)
{
d_msg ("check_fault\n");
return fault;
}
}
//chy 2003-09-02 for test, don't use cache ?????
#if 0
/*search cache no matter MMU enabled/disabled */
cache = mmu_cache_search (state, I_CACHE (), va);
if (cache)
{
*instr = cache->data[va_cache_index (va, I_CACHE ())];
return 0;
}
#endif
/*if MMU disabled or C flag is set alloc cache */
if (MMU_Disabled)
{
c = 1;
pa = va;
}
else
{
c = tlb_c_flag (tlb);
pa = tlb_va_to_pa (tlb, va);
}
//chy 2003-09-03 only read mem, don't use cache now,will change later ????
*instr = mem_read_word (state, pa);
#if 0
//-----------------------------------------------------------
//chy 2003-09-02 for test????
if (pa >= 0xa01c8000 && pa <= 0xa01c8020)
{
printf ("SKYEYE:load_instr: pa %x, va %x,instr %x, R15 %x\n", pa, va,
*instr, state->Reg[15]);
}
//----------------------------------------------------------------------
#endif
return 0;
if (c)
{
int index;
debug_count++;
cache = mmu_cache_alloc (state, I_CACHE (), va, pa);
index = va_cache_index (va, I_CACHE ());
*instr = cache->data[va_cache_index (va, I_CACHE ())];
}
else
*instr = mem_read_word (state, pa);
return 0;
};
static fault_t
xscale_mmu_read_byte (ARMul_State * state, ARMword virt_addr,
ARMword * data)
{
//ARMword temp,offset;
fault_t fault;
fault = xscale_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE);
return fault;
}
static fault_t
xscale_mmu_read_halfword (ARMul_State * state, ARMword virt_addr,
ARMword * data)
{
//ARMword temp,offset;
fault_t fault;
fault = xscale_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE);
return fault;
}
static fault_t
xscale_mmu_read_word (ARMul_State * state, ARMword virt_addr,
ARMword * data)
{
return xscale_mmu_read (state, virt_addr, data, ARM_WORD_TYPE);
}
static fault_t
xscale_mmu_read (ARMul_State * state, ARMword va, ARMword * data,
ARMword datatype)
{
fault_t fault;
// rb_entry_t *rb;
tlb_entry_t *tlb;
cache_line_t *cache;
ARMword pa, real_va, temp, offset;
//chy 2003-09-02 for test ????
static unsigned chyst1 = 0, chyst2 = 0;
d_msg ("va = %x\n", va);
va = mmu_pid_va_map (va);
real_va = va;
/*if MMU disabled, memory_read */
if (MMU_Disabled)
{
//*data = mem_read_word(state, va);
if (datatype == ARM_BYTE_TYPE)
*data = mem_read_byte (state, va);
else if (datatype == ARM_HALFWORD_TYPE)
*data = mem_read_halfword (state, va);
else if (datatype == ARM_WORD_TYPE)
*data = mem_read_word (state, va);
else
{
printf ("SKYEYE:1 xscale_mmu_read error: unknown data type %d\n",
datatype);
exit (-1);
}
return 0;
}
/*align check */
if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned))
{
d_msg ("align\n");
return ALIGNMENT_FAULT;
} // else
va &= ~(WORD_SIZE - 1);
/*translate va to tlb */
fault = translate (state, va, D_TLB (), &tlb);
if (fault)
{
d_msg ("translate\n");
return fault;
}
/*check access permission */
fault = check_access (state, va, tlb, 1);
if (fault)
return fault;
#if 0
//------------------------------------------------
//chy 2003-09-02 for test only ,should commit ????
if (datatype == ARM_WORD_TYPE)
{
if (real_va >= 0xffff0000 && real_va <= 0xffff0020)
{
pa = tlb_va_to_pa (tlb, va);
*data = mem_read_word (state, pa);
chyst1++;
printf
("**SKYEYE:mmu_read word %d: pa %x, va %x, data %x, R15 %x\n",
chyst1, pa, real_va, *data, state->Reg[15]);
/*
cache==mmu_cache_search(state,MAIN_D_CACHE(),va);
if(cache){
*data = cache->data[va_cache_index(va, MAIN_D_CACHE())];
printf("cached data %x\n",*data);
}else printf("no cached data\n");
*/
}
}
//-------------------------------------------------
#endif
#if 0
/*search in read buffer */
rb = mmu_rb_search (RB (), va);
if (rb)
{
if (rb->fault)
return rb->fault;
*data = rb->data[(va & (rb_masks[rb->type] - 1)) >> WORD_SHT];
goto datatrans;
//return 0;
};
#endif
/*2004-07-19 chy: add support of xscale MMU CacheDisabled option */
if (MMU_CacheDisabled)
{
//if(1){ can be used to test cache error
/*get phy_addr */
pa = tlb_va_to_pa (tlb, real_va);
if (datatype == ARM_BYTE_TYPE)
*data = mem_read_byte (state, pa);
else if (datatype == ARM_HALFWORD_TYPE)
*data = mem_read_halfword (state, pa);
else if (datatype == ARM_WORD_TYPE)
*data = mem_read_word (state, pa);
else
{
printf
("SKYEYE:MMU_CacheDisabled xscale_mmu_read error: unknown data type %d\n",
datatype);
exit (-1);
}
return 0;
}
/*search main cache */
cache = mmu_cache_search (state, MAIN_D_CACHE (), va);
if (cache)
{
*data = cache->data[va_cache_index (va, MAIN_D_CACHE ())];
#if 0
//------------------------------------------------------------------------
//chy 2003-09-02 for test only ,should commit ????
if (real_va >= 0xffff0000 && real_va <= 0xffff0020)
{
pa = tlb_va_to_pa (tlb, va);
chyst2++;
printf
("**SKYEYE:mmu_read wordk:cache %d: pa %x, va %x, data %x, R15 %x\n",
chyst2, pa, real_va, *data, state->Reg[15]);
}
//-------------------------------------------------------------------
#endif
goto datatrans;
//return 0;
}
//chy 2003-08-24, now maybe we don't need minidcache ????
#if 0
/*search mini cache */
cache = mmu_cache_search (state, MINI_D_CACHE (), va);
if (cache)
{
*data = cache->data[va_cache_index (va, MINI_D_CACHE ())];
goto datatrans;
//return 0;
}
#endif
/*get phy_addr */
pa = tlb_va_to_pa (tlb, va);
//chy 2003-08-24 , in xscale it means what ?????
#if 0
if ((pa >= 0xe0000000) && (pa < 0xe8000000))
{
if (tlb_c_flag (tlb))
{
if (tlb_b_flag (tlb))
{
mmu_cache_soft_flush (state, MAIN_D_CACHE (), pa);
}
else
{
mmu_cache_soft_flush (state, MINI_D_CACHE (), pa);
}
}
return 0;
}
#endif
//chy 2003-08-24, check phy addr
//ywc 2004-11-30, inactive this check because of using 0xc0000000 as the framebuffer start address
/*
if(pa >= 0xb0000000){
printf("SKYEYE:xscale_mmu_read: phy address 0x%x error,reg[15] 0x%x\n",pa,state->Reg[15]);
return 0;
}
*/
//chy 2003-08-24, now maybe we don't need wb ????
#if 0
/*if Buffer, drain Write Buffer first */
if (tlb_b_flag (tlb))
mmu_wb_drain_all (state, WB ());
#endif
/*alloc cache or mem_read */
if (tlb_c_flag (tlb) && MMU_DCacheEnabled)
{
cache_t *cache_t;
if (tlb_b_flag (tlb))
cache_t = MAIN_D_CACHE ();
else
cache_t = MINI_D_CACHE ();
cache = mmu_cache_alloc (state, cache_t, va, pa);
*data = cache->data[va_cache_index (va, cache_t)];
}
else
{
//*data = mem_read_word(state, pa);
if (datatype == ARM_BYTE_TYPE)
*data = mem_read_byte (state, pa | (real_va & 3));
else if (datatype == ARM_HALFWORD_TYPE)
*data = mem_read_halfword (state, pa | (real_va & 2));
else if (datatype == ARM_WORD_TYPE)
*data = mem_read_word (state, pa);
else
{
printf ("SKYEYE:2 xscale_mmu_read error: unknown data type %d\n",
datatype);
exit (-1);
}
return 0;
}
datatrans:
if (datatype == ARM_HALFWORD_TYPE)
{
temp = *data;
offset = (((ARMword) state->bigendSig * 2) ^ (real_va & 2)) << 3; /* bit offset into the word */
*data = (temp >> offset) & 0xffff;
}
else if (datatype == ARM_BYTE_TYPE)
{
temp = *data;
offset = (((ARMword) state->bigendSig * 3) ^ (real_va & 3)) << 3; /* bit offset into the word */
*data = (temp >> offset & 0xffL);
}
end:
return 0;
}
static fault_t
xscale_mmu_write_byte (ARMul_State * state, ARMword virt_addr, ARMword data)
{
return xscale_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE);
}
static fault_t
xscale_mmu_write_halfword (ARMul_State * state, ARMword virt_addr,
ARMword data)
{
return xscale_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE);
}
static fault_t
xscale_mmu_write_word (ARMul_State * state, ARMword virt_addr, ARMword data)
{
return xscale_mmu_write (state, virt_addr, data, ARM_WORD_TYPE);
}
static fault_t
xscale_mmu_write (ARMul_State * state, ARMword va, ARMword data,
ARMword datatype)
{
tlb_entry_t *tlb;
cache_line_t *cache;
cache_t *cache_t;
int b;
ARMword pa, real_va, temp, offset;
fault_t fault;
ARMword index;
//chy 2003-09-02 for test ????
// static unsigned chyst1=0,chyst2=0;
d_msg ("va = %x, val = %x\n", va, data);
va = mmu_pid_va_map (va);
real_va = va;
if (MMU_Disabled)
{
//mem_write_word(state, va, data);
if (datatype == ARM_BYTE_TYPE)
mem_write_byte (state, va, data);
else if (datatype == ARM_HALFWORD_TYPE)
mem_write_halfword (state, va, data);
else if (datatype == ARM_WORD_TYPE)
mem_write_word (state, va, data);
else
{
printf ("SKYEYE:1 xscale_mmu_write error: unknown data type %d\n",
datatype);
exit (-1);
}
return 0;
}
/*align check */
if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned))
{
d_msg ("align\n");
return ALIGNMENT_FAULT;
} //else
va &= ~(WORD_SIZE - 1);
/*tlb translate */
fault = translate (state, va, D_TLB (), &tlb);
if (fault)
{
d_msg ("translate\n");
return fault;
}
/*tlb check access */
fault = check_access (state, va, tlb, 0);
if (fault)
{
d_msg ("check_access\n");
return fault;
}
/*2004-07-19 chy: add support for xscale MMU_CacheDisabled */
if (MMU_CacheDisabled)
{
//if(1){ can be used to test the cache error
/*get phy_addr */
pa = tlb_va_to_pa (tlb, real_va);
if (datatype == ARM_BYTE_TYPE)
mem_write_byte (state, pa, data);
else if (datatype == ARM_HALFWORD_TYPE)
mem_write_halfword (state, pa, data);
else if (datatype == ARM_WORD_TYPE)
mem_write_word (state, pa, data);
else
{
printf
("SKYEYE:MMU_CacheDisabled xscale_mmu_write error: unknown data type %d\n",
datatype);
exit (-1);
}
return 0;
}
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