armvirt.c

这是Skyeye 0.9 版本的源代码

\***************************************************************************/

ARMword
ARMul_LoadWordS (ARMul_State * state, ARMword address)
{
  state->NumScycles++;

  return ARMul_ReadWord (state, address);
}

/***************************************************************************\
*                      Load Word, Non Sequential Cycle                      *
\***************************************************************************/

ARMword
ARMul_LoadWordN (ARMul_State * state, ARMword address)
{
  state->NumNcycles++;

  return ARMul_ReadWord (state, address);
}

/***************************************************************************\
*                     Load Halfword, (Non Sequential Cycle)                 *
\***************************************************************************/

ARMword
ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
{
  ARMword data;
  fault_t fault;

  state->NumNcycles++;
  fault = GetHalfWord (state, address, &data);

  if (fault)
    {
      state->mmu.fault_status =
	(fault | (state->mmu.last_domain << 4)) & 0xFF;
      state->mmu.fault_address = address;
      ARMul_DATAABORT (address);
      return ARMul_ABORTWORD;
    }
  else
    {
      ARMul_CLEARABORT;
    }

  return data;

}

#if 0
ARMword
ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
{
  ARMword temp, offset;

  state->NumNcycles++;

  temp = ARMul_ReadWord (state, address);
  offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3;	/* bit offset into the word */

  return (temp >> offset) & 0xffff;
}
#endif

/***************************************************************************\
*                      Read Byte (but don't tell anyone!)                   *
\***************************************************************************/

ARMword
ARMul_ReadByte (ARMul_State * state, ARMword address)
{
  ARMword data;
  fault_t fault;

  fault = GetByte (state, address, &data);

  if (fault)
    {
      state->mmu.fault_status =
	(fault | (state->mmu.last_domain << 4)) & 0xFF;
      state->mmu.fault_address = address;
      ARMul_DATAABORT (address);
      return ARMul_ABORTWORD;
    }
  else
    {
      ARMul_CLEARABORT;
    }

  return data;

}

#if 0
ARMword
ARMul_ReadByte (ARMul_State * state, ARMword address)
{
  ARMword temp, offset;

  temp = ARMul_ReadWord (state, address);
  offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;	/* bit offset into the word */

  return (temp >> offset & 0xffL);
}
#endif

/***************************************************************************\
*                     Load Byte, (Non Sequential Cycle)                     *
\***************************************************************************/

ARMword
ARMul_LoadByte (ARMul_State * state, ARMword address)
{
  state->NumNcycles++;

  return ARMul_ReadByte (state, address);
}

/***************************************************************************\
*                     Write Word (but don't tell anyone!)                   *
\***************************************************************************/

void
ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data)
{
  fault_t fault;

#ifdef ABORTS
  if (address >= LOWABORT && address < HIGHABORT)
    {
      ARMul_DATAABORT (address);
      return;
    }
  else
    {
      ARMul_CLEARABORT;
    }
#endif

  fault = PutWord (state, address, data);
  if (fault)
    {
      state->mmu.fault_status =
	(fault | (state->mmu.last_domain << 4)) & 0xFF;
      state->mmu.fault_address = address;
      ARMul_DATAABORT (address);
      return;
    }
  else
    {
      ARMul_CLEARABORT;
    }
}

/***************************************************************************\
*                       Store Word, Sequential Cycle                        *
\***************************************************************************/

void
ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data)
{
  state->NumScycles++;

  ARMul_WriteWord (state, address, data);
}

/***************************************************************************\
*                       Store Word, Non Sequential Cycle                        *
\***************************************************************************/

void
ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data)
{
  state->NumNcycles++;

  ARMul_WriteWord (state, address, data);
}

#if 0
/***************************************************************************\
*                    test the virtual addr is or isn't IO address           *
\***************************************************************************/
//chy: 2003-05-26
//extern skyeye_config_t skyeye_config;
int
ARMul_notIOaddr (ARMul_State * state, ARMword address)
{
  if (!(state->mmu.control & CONTROL_MMU))
    {
      //chy: now is hacking, not very complete
      if (address >= skyeye_config.ioaddr.addr_begin
	  && address <= skyeye_config.ioaddr.addr_end)
	return 0;
      else
	return 1;
    }
  else
    {
      printf ("ARMul_noIOaddr for mmuenable should do in the future!!!\n");
      exit (-1);
    }

}
#endif

/***************************************************************************\
*                    Store HalfWord, (Non Sequential Cycle)                 *
\***************************************************************************/

void
ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data)
{
  fault_t fault;
  state->NumNcycles++;
  fault = PutHalfWord (state, address, data);
  if (fault)
    {
      state->mmu.fault_status =
	(fault | (state->mmu.last_domain << 4)) & 0xFF;
      state->mmu.fault_address = address;
      ARMul_DATAABORT (address);
      return;
    }
  else
    {
      ARMul_CLEARABORT;
    }
}

#if 0
void
ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data)
{
  ARMword temp, offset;

  state->NumNcycles++;

#ifdef VALIDATE
  if (address == TUBE)
    {
      if (data == 4)
	state->Emulate = FALSE;
      else
	(void) putc ((char) data, stderr);	/* Write Char */
      return;
    }
#endif
  //chy 2003-05-26, if the addr is io addr, then there is error(read io addr maybe change the io register value), so i change it. but now only support mmuless. for mmuenable, it will change again.
  if (ARMul_notIOaddr (state, address))
    {
      temp = ARMul_ReadWord (state, address);
    }
  else
    {
      temp = 0;
    }

  offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3;	/* bit offset into the word */

  PutWord (state, address,
	   (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset));
}
#endif

/***************************************************************************\
*                     Write Byte (but don't tell anyone!)                   *
\***************************************************************************/
//chy 2003-07-10, add real write byte fun
void
ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data)
{
  fault_t fault;
  fault = PutByte (state, address, data);
  if (fault)
    {
      state->mmu.fault_status =
	(fault | (state->mmu.last_domain << 4)) & 0xFF;
      state->mmu.fault_address = address;
      ARMul_DATAABORT (address);
      return;
    }
  else
    {
      ARMul_CLEARABORT;
    }
}

#if 0
void
__ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data)
{
  ARMword temp, offset;

  //chy 2003-05-26, if the addr is io addr, then there is error(read io addr maybe change the io register value), so i change it. but now only support mmuless. for mmuenable, it will change again.
  if (ARMul_notIOaddr (state, address))
    {
      temp = ARMul_ReadWord (state, address);
    }
  else
    {
      temp = 0;
    }

  offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;	/* bit offset into the word */

  PutWord (state, address,
	   (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset));
}
#endif

/***************************************************************************\
*                    Store Byte, (Non Sequential Cycle)                     *
\***************************************************************************/

void
ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data)
{
  state->NumNcycles++;

#ifdef VALIDATE
  if (address == TUBE)
    {
      if (data == 4)
	state->Emulate = FALSE;
      else
	(void) putc ((char) data, stderr);	/* Write Char */
      return;
    }
#endif

  ARMul_WriteByte (state, address, data);
}

/***************************************************************************\
*                   Swap Word, (Two Non Sequential Cycles)                  *
\***************************************************************************/

ARMword
ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data)
{
  ARMword temp;

  state->NumNcycles++;

  temp = ARMul_ReadWord (state, address);

  state->NumNcycles++;

  PutWord (state, address, data);

  return temp;
}

/***************************************************************************\
*                   Swap Byte, (Two Non Sequential Cycles)                  *
\***************************************************************************/

ARMword
ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data)
{
  ARMword temp;

  temp = ARMul_LoadByte (state, address);
  ARMul_StoreByte (state, address, data);

  return temp;
}

/***************************************************************************\
*                             Count I Cycles                                *
\***************************************************************************/

void
ARMul_Icycles (ARMul_State * state, unsigned number,
	       ARMword address ATTRIBUTE_UNUSED)
{
  state->NumIcycles += number;
  ARMul_CLEARABORT;
}

/***************************************************************************\
*                             Count C Cycles                                *
\***************************************************************************/

void
ARMul_Ccycles (ARMul_State * state, unsigned number,
	       ARMword address ATTRIBUTE_UNUSED)
{
  state->NumCcycles += number;
  ARMul_CLEARABORT;
}