wdtimer.asm

aduc812精典源代码下载,适合初学者

;********************************************************************
;
; Author        : ADI - Apps            www.analog.com/MicroConverter
;
; Date          : 28 May 1999
;
; File          : WDtimer.asm
;
; Hardware      : ADuC812
;
; Description   : Demonstrates use of the on-chip watchdog timer.
;                 In normal operation, WD timer is refreshed by code
;                 every 100ms, as indicated by a flashing LED.  in a
;                 runaway code condition (which can be simulated here
;                 by pressing the INT0 button on the eval board) code
;                 fails to refresh WD bits, and WD timer generates a
;                 reset after a user selected time-out period (from
;                 16ms to 2048ms) has elapsed.  the time-out period
;                 in this routine is 2.048ms for visual clarity.
;
;                 note: be sure to remove the PSEN pull-down (LK3)
;                       before allowing watchdog to time-out, or
;                       you'll end up in serial download mode again
;                       rather than recovering normal code execution.
;
;********************************************************************

$MOD812                         ; Use 8052&ADuC812 predefined symbols

LED     EQU     P3.4            ; P3.4 drives red LED on eval board
ERROR   EQU     F0              ; the 'ERROR' flag is used here to
                                ; simulate an erroneous command that
                                ; sends code into an unknown state

;____________________________________________________________________
                                                  ; BEGINNING OF CODE
CSEG

ORG 0000h

        JMP     MAIN            ; jump to main program
;____________________________________________________________________
                                             ; INTERRUPT VECTOR SPACE
ORG 0003h ;  (INT0 ISR)

        SETB    ERROR           ; simulate an error condition..
                                ; ..when INT0 button is pressed
        RETI

;====================================================================
                                                       ; MAIN PROGRAM
ORG 004Bh

MAIN:

; ENABLE INTERRUPT TO TRIGGER SIMULATED ERROR CONDITION...

        SETB    IT0             ; make INT0 edge triggered
        SETB    EA              ; enable interrupts
        SETB    EX0             ; enable INT0 (button on eval board)
        CLR     ERROR           ; simulate error free operation

; SET UP WATCHDOG TIMER...

        MOV     WDCON,#0E0h     ; 2.048 second timeout period
        SETB    WDE             ; enable watchdog timer

;  from this point forward, watchdog bits must be refreshed every
;  2.048 seconds or less.  if they are not, watchdog timer will
;  generate a reset.

; THE BELOW LOOP REPRESENTS NORMAL CODE EXECUTION...

FLASH:  CPL     LED             ; blink (complement) the red LED
        CALL    DELAY           ; delay 100ms
        SETB    WDR1            ; refresh watchdog timer..
        SETB    WDR2            ; ..bits must be set in this order
        JNB     ERROR,FLASH     ; jump if 'ERROR' flag is not set

; THE BELOW ENDLESS LOOP REPRESENTS RUN-AWAY CODE EXECUTION...

        JMP     $               ; this endless loop is used to
                                ; represent an unknown state of
                                ; program execution

;  program will sit in the above endless loop until the watchdog
;  period (2048ms) has elapsed, at which time a reset will be
;  generated by the watchdog timer, thereby recovering the chip to
;  resume normal code execution.

;____________________________________________________________________
                                                         ; SUBROUTINE

DELAY:                          ; delay 100ms

        MOV     R7,#200         ; 200 * 500us = 100ms
DLY1:   MOV     R6,#229         ; 229 * 2.17us = 500us
        DJNZ    R6,$            ; sit here for 500us
        DJNZ    R7,DLY1         ; repeat 200 times (100ms total)
        RET

;____________________________________________________________________

END