vga.srr

vga显示驱动,在EDA中实现对VGA显示器的驱动控制。

$ Start of Compile
#Fri Dec 30 16:52:18 2005

Synplicity VHDL Compiler, version Compilers 7.3, Build 036R, built Oct  1 2003
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

Synthesizing work.vga.a
Post processing for work.vga.a
@W:"D:\yjsj\vga\vga.vhd":62:0:62:1|Latch generated from process for signal pixel_row(10 downto 0), probably caused by a missing assignment in an if or case stmt
@W:"D:\yjsj\vga\vga.vhd":55:0:55:1|Latch generated from process for signal pixel_column(10 downto 0), probably caused by a missing assignment in an if or case stmt
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Triscend Technology Mapper, version 7.3, Build 206R, built Sep 25 2003
Copyright (C) 1994-2003, Synplicity Inc.  All Rights Reserved
List of partitions to map:
   view:work.VGA(a)


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Dec 30 16:52:19 2005
#


Top view:               VGA
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N| Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]


---------------------------------------
Resource Usage Report 

Mapping to part: ta7s20

LUT count: 35
Latch bits: 22
----------------
Usage details
LUT4 : 33
LUT5 : 1
---------------------------------------

Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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