📄 vgaf.srr
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$ Start of Compile
#Fri Dec 23 16:58:52 2005
Synplicity VHDL Compiler, version Compilers 7.3, Build 036R, built Oct 1 2003
Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved
VHDL syntax check successful!
Compiler output is up to date. No re-compile necessary
Synthesizing work.vga.a
Post processing for work.vga.a
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################[
Synplicity Triscend Technology Mapper, version 7.3, Build 206R, built Sep 25 2003
Copyright (C) 1994-2003, Synplicity Inc. All Rights Reserved
List of partitions to map:
view:work.VGA(a)
@N:"d:\yjsj\vga\vgaf.vhd":18:17:18:23|Found counter in view:work.VGA(a) inst z[9:0]
@W:|Removing instance un8_h_count_1 of view:DECOMP.PM_ADDC__0_10(DECOMP) because there are no references to its outputs
@W:"d:\yjsj\vga\vgaf.vhd":18:17:18:23|Removing sequential instance z[9:0] of view:PrimLib.counter(prim) because there are no references to its outputs
Found clock VGA|clock_25Mhz with period 1000.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Dec 23 16:58:53 2005
#
Top view: VGA
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N| Clock constraints cover only FF-to-FF paths associated with the clock.
Performance Summary
*******************
Worst slack in design: 986.694
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------
VGA|clock_25Mhz 1.0 MHz 75.2 MHz 1000.000 13.306 986.694 inferred default_clkgroup
=====================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
--------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
--------------------------------------------------------------------------------------------------------------------------
VGA|clock_25Mhz VGA|clock_25Mhz | 1000.000 986.694 | No paths - | No paths - | No paths -
==========================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: VGA|clock_25Mhz
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------
z.I_18 VGA|clock_25Mhz DFFC Q z[6] 1.223 986.694
z.I_20 VGA|clock_25Mhz DFFC Q z[5] 1.223 986.936
z.I_17 VGA|clock_25Mhz DFFC Q z[3] 1.223 986.956
z.I_12 VGA|clock_25Mhz DFFC Q z[2] 1.223 987.073
z.I_14 VGA|clock_25Mhz DFFC Q z[9] 1.223 988.444
z.I_13 VGA|clock_25Mhz DFFC Q z[4] 1.223 988.633
z.I_19 VGA|clock_25Mhz DFFC Q z[7] 1.223 988.776
z.I_11 VGA|clock_25Mhz DFFC Q z[8] 1.223 989.295
h_count[0] VGA|clock_25Mhz DFFC Q h_count[0] 1.223 991.414
h_count[2] VGA|clock_25Mhz DFFC Q h_count[2] 1.223 991.615
======================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------
z.I_14 VGA|clock_25Mhz DFFC D z.sum_bus[9] 999.370 986.694
z.I_11 VGA|clock_25Mhz DFFC D z.sum_bus[8] 999.370 987.089
z.I_19 VGA|clock_25Mhz DFFC D z.sum_bus[7] 999.370 987.484
z.I_18 VGA|clock_25Mhz DFFC D z.sum_bus[6] 999.370 987.879
z.I_20 VGA|clock_25Mhz DFFC D z.sum_bus[5] 999.370 988.274
z.I_13 VGA|clock_25Mhz DFFC D z.sum_bus[4] 999.370 988.669
z.I_17 VGA|clock_25Mhz DFFC D z.sum_bus[3] 999.370 989.064
z.I_12 VGA|clock_25Mhz DFFC D z.sum_bus[2] 999.370 989.459
z.I_15 VGA|clock_25Mhz DFFC D z.sum_bus[1] 999.370 989.854
z.I_16 VGA|clock_25Mhz DFFC D z.sum_bus[0] 999.370 991.242
=======================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: 0.630
= Required time: 999.370
- Propagation time: 12.676
= Slack (critical) : 986.694
Number of logic level(s): 13
Starting point: z.I_18 / Q
Ending point: z.I_14 / D
The start point is clocked by VGA|clock_25Mhz [rising] on pin CK
The end point is clocked by VGA|clock_25Mhz [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
z.I_18 DFFC Q Out 1.223 1.223 -
z[6] Net - - - - 5
G_156_199 LUT4 I1 In 0.000 1.223 -
G_156_199 LUT4 O Out 1.754 2.977 -
N_275 Net - - - - 1
I_141_i_or2 LUT5 I1 In 0.000 2.977 -
I_141_i_or2 LUT5 O Out 2.264 5.241 -
N_211 Net - - - - 3
N_211_i INV I In 0.000 5.241 -
N_211_i INV O Out 1.512 6.753 -
N_211_i Net - - - - 10
z.I_1 ADD1 LD In 0.000 6.753 -
z.I_1 ADD1 CO Out 2.234 8.987 -
z.carry_bus[0] Net - - - - 1
z.I_2 ADD1 CI In 0.000 8.987 -
z.I_2 ADD1 CO Out 0.395 9.382 -
z.carry_bus[1] Net - - - - 1
z.I_5 ADD1 CI In 0.000 9.382 -
z.I_5 ADD1 CO Out 0.395 9.777 -
z.carry_bus[2] Net - - - - 1
z.I_8 ADD1 CI In 0.000 9.777 -
z.I_8 ADD1 CO Out 0.395 10.172 -
z.carry_bus[3] Net - - - - 1
z.I_4 ADD1 CI In 0.000 10.172 -
z.I_4 ADD1 CO Out 0.395 10.567 -
z.carry_bus[4] Net - - - - 1
z.I_7 ADD1 CI In 0.000 10.567 -
z.I_7 ADD1 CO Out 0.395 10.962 -
z.carry_bus[5] Net - - - - 1
z.I_3 ADD1 CI In 0.000 10.962 -
z.I_3 ADD1 CO Out 0.395 11.357 -
z.carry_bus[6] Net - - - - 1
z.I_6 ADD1 CI In 0.000 11.357 -
z.I_6 ADD1 CO Out 0.395 11.752 -
z.carry_bus[7] Net - - - - 1
z.I_10 ADD1 CI In 0.000 11.752 -
z.I_10 ADD1 CO Out 0.395 12.147 -
z.carry_bus[8] Net - - - - 1
z.I_9 ADD1 CI In 0.000 12.147 -
z.I_9 ADD1 SUM Out 0.529 12.676 -
z.sum_bus[9] Net - - - - 1
z.I_14 DFFC D In 0.000 12.676 -
=============================================================================
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report
Mapping to part: ta7s20
LUT count: 46
Register bits: 49
----------------
Usage details
LUT4 : 24
LUT5 : 1
ADD1 : 20
INV : 1
---------------------------------------
Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################]
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