traplog.tlg

来自「vga显示驱动,在EDA中实现对VGA显示器的驱动控制。」· TLG 代码 · 共 12 行

Synthesizing work.top.gen
Synthesizing work.upcntr.cell_level
@W:"syng0a03416":81:12:81:15|Unbound component ADD1 mapped to black box
@W:"syng0a03416":85:12:85:15|Unbound component DFFC mapped to black box
Synthesizing work.dffc.syn_black_box
Post processing for work.dffc.syn_black_box
Synthesizing work.add1.syn_black_box
Post processing for work.add1.syn_black_box
Post processing for work.upcntr.cell_level
@W:"syng0a03416":76:7:76:10|Input updn is unused
Post processing for work.top.gen