📄 traplog.tlg
字号:
Synthesizing work.top.gen
Synthesizing work.upcntr.cell_level
@W:"syng0a03416":81:12:81:15|Unbound component ADD1 mapped to black box
@W:"syng0a03416":85:12:85:15|Unbound component DFFC mapped to black box
Synthesizing work.dffc.syn_black_box
Post processing for work.dffc.syn_black_box
Synthesizing work.add1.syn_black_box
Post processing for work.add1.syn_black_box
Post processing for work.upcntr.cell_level
@W:"syng0a03416":76:7:76:10|Input updn is unused
Post processing for work.top.gen
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -