bootrom.asm

award bios 源代码,喜欢汇编程序及想研究主板BIOS程序的人可以参考哦.我是费了老大的劲才找到的哦.

;	[]===========================================================[]
;
;	NOTICE: THIS PROGRAM BELONGS TO AWARD SOFTWARE INTERNATIONAL(R)
;	        INC. IT IS CONSIDERED A TRADE SECRET AND IS NOT TO BE
;	        DIVULGED OR USED BY PARTIES WHO HAVE NOT RECEIVED
;	        WRITTEN AUTHORIZATION FROM THE OWNER.
;
; 	[]===========================================================[]
;

;----------------------------------------------------------------------------
;Rev	Date	 Name	Description
;----------------------------------------------------------------------------
;R151 	12/24/97 MIL	Added "Chipboot_In_External_Boot_Block" define, for
;			move chipboot code to first 8k Boot Block Area.
;R150A	12/08/97 DRS	Some chipset don't want support run PCI/AGP VGA in bootblock
;R150	12/08/97 DRS	Support 16K_8K_8K_Unit of 2M Flash run PCI/AGP
;			Vga in bootblock
;R146B	12/06/97 MIL	Added Cyrix MediaGXm CPU ID.
;R149	11/17/97 RAY	Add flag for the new CBROM.EXE to distinguish the old
;			BIOS & the new BIOS
;R148	08/07/97 DNL	Return compressed code original size by EDX register
;R147 	07/09/97 MIL	Added Patch to Fix BIOS's in boot block can't boot
;			from FDD (for Media GX86).
;R146A	07/03/97 MIL	Added Cyrix MediaGXm CPU ID.
;R146	07/01/97 MIL	Added Cyrix MediaGXi CPU ID.
;R78A	06/20/97 KVN	Remove Earlyio.asm to another location for avoid
;			BootBlock code space overflow
;R143A	06/17/97 KVN	Should clear bus or some chipset will detect error
;			when no plug DRAM.
;R145	05/29/97 LAW	added "BEEP_FOR_NO_RAM"
;R144	05/21/97 KVN	Fix up beep sound frequence not fix if CPU clock is
;			different when memory, VGA or floppy error during POST
;R143	04/12/97 RCH	Change first 256Kb memory testing method to speed up
;			POST.
;R142	03/28/97 RCH	Fixed system sometimes hang at C6H if Cyrix CPU at
;			75Mhzx2 and NEC/SDRAM module for special defined
;			"PATCH_FOR_PR200_SDRAM"
;R138A	03/25/97 RCH	Restore code modified by R138 , it cause DRAM refresh
;			lost.
;R141	03/25/97 RCH	Change year of copyright from 1996 to 1997
;R140	03/24/97 RCH	Align 16 for label "*BBSS*" searching to speed up
;			booting for 2M flash and Pentium Pro platform.
;R139	03/24/97 RAY	Do not clear the warm boot flag if we support PCI RESET
;R138	03/23/97 TNY	We should not program 8237 and 8254 before DRAM sizing
;			, because it cause DRAM sizing hang randonly.(ex:intel chip)
;R104D	02/14/97 RCH	DX will be destroied and lost CPU ID for non-SMI 486
;			if define SLOW_RTC_PATCH
;R137A	02/14/97 KVN	Fixed no show full screen logo bug on 2M BIOS and you
;			combine logo pattern at first area
;R133A	01/24/96 RCH	Support M2 CPU become standard feature
;R137	01/15/97 KVN	Remove P6 micro code to ROM driver pool from 0E000h
;			POST location
;R136	01/10/97 KVN	Fix CIRRUS LOGIC CL-GD5422-80QC-D VGA card cause system
;			hang while initial in boot block POST.Because it will
;			call 0F000h:0F065h (video vector address).
;R135	01/09/97 RCH	Add support both Pentium Pro and Klamath CPUs in one
;			BIOS. Note: It need 3 swtich in BIOS.CFG
;				BOTH_P6_KLAMATH_CPU	EQU	1
;				KLAMATH_CPU_ONLY	EQU	1
;				P6_BIOS_ONLY		EQU	1
;
;R134	01/09/97 DNL	Add switch Special_Early_Init to invoke Ct_Very_Early_Init
;			code size to small problem.
;R133	12/13/96 RCH	Temporary support M2 CPU, This code must be modified
;			after receiving sample.
;R132	12/11/96 RAY	Add switch Very_Very_Early_Init to invoke Ct_Very_Early_Init
;			for some chipsets to enable the ISA decoding before
;			we access any ISA ports. Note that there are some
;			PCI-To-ISA bridges has a default value of ISA disabled.
;R131	12/11/96 RAY	Add Cyrix Gx86 CPU ID
;R130	12/03/96 RCH	The WB cache problem has been fixed on B0 stepping,so
;			enable WB cache for newer revision of KLAMATH CPUs
;			to speed up POST.
;R104C	11/30/96 TNY	Add "SLOW_RTC_PATCH_Delay" option for 2c4l6r31.bin.
;R104B	11/19/96 TNY	Fix some M/B RTC always failed, so we add some delay
;			to patch it.
;R129A	10/21/96 AVN	Fixed Coding Error, Cause 16K BootBlock Cannot Call
;			Extern_execute1/Extern_execute2
;R129	10/16/96 AVN	To Support Different BootBlock For
;			INTEL 2M EEPROM	: 16K BootBlock
;			SST 2M EEPROM	: 16K BootBlock
;			ATMEL 2M EEPROM	: 16K BootBlock
;			AMD 2M EEPROM	: 16K BootBlock
;			MXIC 2M EEPROM	:  8K BootBlock
;R128	10/09/96 RCH	Added Klamath CPU support
;R127	10/08/96 RCH	Change year of copyright from 1995 to 1996
;R126	10/07/96 RCH	Create a new file "P6UPD.INC" to put P6 micro code
;R125	10/01/96 AVN	Fixed if INTEL 28F002BXT boot fail, for awdflash.exe
;			can detect Enable/Disable_Extra_1MBIOS_Hook Correct.
;R124	09/19/96 RCH	Don't initial KBC if not use KBC to control 2M flash
;R108D	09/04/96 KVN	Fixed awdflash.exe update new BIOS then hang at 0C3h
;			when use INTEL 28F001BX-T flash rom
;R104A	08/23/96 KVN	Change another pattern to check CMOS access ready or not
;			for "2A4KDAKA" and "2A4KDAKB".Because its CMOS default
;			value is 0
;R123	08/21/96 KVN	Move some Boot Block code (0E000-0FFFFh) to external
;			Boot Block (0C000-0DFFFh) area for 2MB BIOS to avoid
;			8K Boot Block size overflow
;R122	08/19/96 KVN	Added 2MB flash 16K boot block support
;R121	08/16/96 KVN	Fixed 2M bios with FULL_SCREEN_LOGO hang at 0c3h bug
;R108C	08/15/96 KVN	Fixed coding mistake
;R120A	07/29/96 RCH	Fixed error coding of R120 , that cause chipset not
;			wrap around for E-segment will enter bootblock.
;			Chipsets like ALI1487/89.
;R120	07/26/96 RCH	Some motherboards (use INTEL's chipset) can not read
;			data in E-segment if both BIOSCS# and ISA have ROM
;			decoding.
;R119	07/22/96 RCH	The production revision of P6 is 0617H , so swap the
;			patch codes for 0617H & 0612H, put 0617H in flash
;			block and let end user to update by INTEL's utility
;R118	07/20/96 RAY	For supporting 2M flash, some M/B vendors connect
;			the flash A17 to KB controller's pin. Thus we have
;			to enable KB controller before we can program the
;			A17(KB pin) to low so as to access the extra 1M
;			ROM.
;R117	07/08/96 KVN	Change P6 data pool offset and size.
;R116	07/01/96 KVN	Support 2MB ROM BIOS
;R115	06/17/96 RCH	Some super I/Os' FDD is disabled , BIOS's in boot
;			block need to enable it for booting access, otherwise
;			can not boot from FDD to update normal BIOS.(chips
;			like SMC669,UMC8669 ...)
;R114	06/17/96 RCH	Fixed bootblock BIOS for P6 can not boot from FDD
;			to update normal BIOS.
;R113	06/01/96 RCH	Put code into alignment to prevent system hang at
;			memory size for higher speed CPU
;R111B	05/30/96 AVN	For Custom Chipset (LYNX ect ...) Issue Hardware Reset
;			And Memory Bank Value Default is None, Cause Lose
;			WarmBoot flag, So Move the Function After Memory Sizing.
;R111A	05/25/96 RCH	Clear CMOS location of PCI reset flag as soon as
;			possible to prevent wrong warm booting by last
;			uncompleted booting.
;R112	05/25/96 RCH	Rewrite code of first 256kb memory testing routine
;			to reduce time for P6 system
;R106A	05/13/96 RCH	More delay for 6x86 CPU to fix L2 cache can not found
;			sometimes.
;R111	05/11/96 RCH	Added PCI reset function support to prevent PCI master
;			devices hang while warm booting.
;R110	05/02/96 DNL	Added codes for notebook power management
;R108B	04/30/96 KVN	Don't destroy AX otherwise only decompress two compressed
;			code if BIOS compressed size below 64K
;R107A	04/24/96 RIC	Add define 'VLSI_Special_Reset_Delay' for Special
;			delay For VLSI Lynx chipset,because using Cyrix CPU
;			will halt in post_code '05' for some mainboard.
;R108A	04/23/96 KVN	Added some code to compatible old BIOS version for INTEL
;			flash ROM update
;R109	04/22/96 KVN	Fixed execute warm boot routine when press CTRL-ALT-Del
;			then sudden press hard reset switch or power off and
;			power on right now
;R108	04/22/96 KVN	Fixed BIOS checksum error if BIOS update to support DMI
;			function on INTEL flash rom
;R107	04/12/96 RIC	Special delay For VLSI Lynx chipset,because using
;			Cyrix CPU will halt in post_code '05'.
;R106	04/11/96 RCH	Some chipsets (like i430VX) sometimes hang up after
;			memory sizing if 6X86 133Mhz used. Add a delay loop
;			to fix it if define DELAY_FOR_6X86_PWRON
;R105	04/09/96 KVN	Added P6 BIOS update feature
;R104	04/02/96 RCH	Fixed some RTCs (like SAMSUNG/6818A) ready too slow
;			while power on, it cause CPU type can not be recorded
;			properly. please define SLOW_RTC_PATCH.
;R102C	03/28/96 KVN	Fixed R102B only for define FULL_SCREEN_LOGO
;R102B	03/27/96 KVN	Fixed bug for execute awdflash.exe v5.1 hang if support
;			full-page 640X464 logo
;R103	03/14/96 KVN	Fixed always execute bootrom code of memory sizing
;R102A	02/15/96 KVN	Fixed bug for execute awdflash.exe hang
;R102	02/14/96 KVN	Added 640x480 logo display
;R101	02/08/96  KVN	Change BIOS revision for setup default display title
;			string of MODBIN.EXE
;R100	02/02/96 RCH	The ALI/152X chipset should set chipset register to
;			turn on L1 cache and this bit should be set after
;			CPU L1 cache is turon.
;R99	02/01/96 RIC    Special Reset For VLSI Lynx chipset.
;R98	12/12/95 RCH	Special patch for ORION/PnP
;R97	12/09/11 RCH	P6 don't have 16bytes buffer , so change method for
;			supporting PnP/ESCD.
;R96	12/07/95 TNY	Add QUALIFY_L2_CACHE_ON_DECOMPRESS for VIA570 special.
;R95	12/04/95 RCH	Cyrix have a wrong CPU ID and it need BIOS to support
;			it.
;R94	11/23/95 KVN	Fixed system hang if modify ct_memory_presence routine
;R93	11/17/95 RCH	Don't use E1H to do delay, use NEWIODELAY instead
;R92    10/18/95 KVN	Added revision number for modbin
;R91    10/18/95 RCH	Added Cyrix 5x86 4x clock (133Mhz) support
;R90	10/18/95 KVN	Added MXIC FLASH PnP feature support
;R89	09/13/95 RCH	Added TI486 DX4 CPU support , the value is 81H in DIR0
;			because this CPU is same as CxDx4 , so use same CPU
;			value in CMOS
;R88	07/06/95 KVN	Disable M1 LINBRST bit of CCR3 before turn on cpu_cache
;R87	07/05/95 RCH	Some chipsets can not turn on L1 cache alone with
;			some special cases.
;R86	06/16/95 RAY	Add individual control switches to each level CPU
;R85	06/14/95 RCH	Remove some CPUs table and detected them with CPUID
;			instruction in CPU.ASM
;R84	06/14/95 KVN	Fixed checksum bug when be compressed size over 64KB
;R63A	06/14/95 RCH	Fixed error coding for 586 CPU
;R83	06/13/95 RCH	Some M/Bs (like VIA/570) failed on warm boot or exit
;			from setup while M1 CPU plugged and linear burst is
;			on.
;R73A	06/12/95 DNL	Move linear burst function to CPU.ASM
;R82	06/09/95 DNL	Added Cyrix M1 CPU 4 clock mode support
;R81	06/07/95 RCH	Added INTEL P55CT support
;R80    06/05/95 RCH	Added INTEL P6 CPU support
;R79	05/31/95 RAY	Some Cyrix CPU return ID with value 00h, e.g. M6
;			engineering samples
;R78	05/30/95 RCH	Some super IO contain RTC & KBC should be programmed
;			just after power on
;R77	05/24/95 RCH	Move codes to atorgs.asm due to some M/Bs hang up
;			while warmboot from OS2 for WB CPU
;R76	05/22/95 KVN	Add Expand subroutine offset for AWDFLASH.EXE utility
;R75	05/20/95 RAY	Add Cyrix DX4 support
;R74	05/17/95 AVN	Fixed Routine Address Had Change If Modify Chiprun.asm
;			And FLASH_ROUTINE_HEAD Was Index Old Address Because
;			Can't Rewrite By Use INTEL BOOTBLOCK ROM.
;			FLASH_ROUTINE_HEAD Move To Chiprun.asm
;R73	05/09/95 DNL	Added Cyrix M1 CPU linear burst function support
;R72	04/27/95 KVN	Fixed BootBlock ROM Ckecksum Fail Boot From FDD Can't
;			Run Autoexec.bat.
;R71A	04/27/95 DNL	Fixed Cyrix CPU type detection incorrect bug
;R71	04/17/95 RCH	Support Cyrix M1 CPU become stanard feature, also
;			rewrite CPU detection for M6/M7
;R70	03/15/95 DNL	Added CYRIX M9 CPU support
;R69	03/15/95 RCH	Don't issue memory write before memory sizing ,
;			otherwise UMC/890 system hang at POST_5s after
;			hardware reset with SST flash ROM.
;R68	03/10/95 KVN	Fix keyboard service (int 16) error
;R67	02/28/95 DNL	Don't destroy ES register during expand compression BIOS
;			, because that can't find VGA BIOS
;R66	02/23/95 AVN	Added New Flash Utility in chiprun.asm
;R65	02/23/95 KVN	"sti" when call int16 func0
;R64	02/07/95 KVN	Boot block bios support Keyboard
;R63	01/10/95 RAY	Add No_386_Support & No_586_Support option
;R61	01/09/95 RCH	Added INTEL P5T CPU support,it's P5 overdrive
;R60	01/07/95 RCH	Added INTEL P54CT CPU support,it's P54C overdrive
;R59	01/06/95 DNL	Added U5 non_cache CPU support
;R58	12/29/94 RCH	Added more stepping number for IBM 486DL3 CPU
;R54	11/30/94 RCH	Added CYRIX M1 CPU support. There are four clock modes
;			of this CPU , we don't support 4/1 mode now.
;R52A	11/30/94 RCH	Also disable PENTIUM parity check

		PAGE	56,132
		TITLE	BOOTROM  -- 386 ROM/BIOS BASE
.386P
;[]-----------------------------------[]
;
;   Award Software 386/486 BIOS
;    Base + Initialization Rtns
;   Initial Revision 17-Apr-1990
;
;[]-----------------------------------[]

		INCLUDE BIOS.CFG
		INCLUDE COMMON.MAC
		INCLUDE ATORGS.MAC
		INCLUDE POST.MAC

		INCLUDE CMOS.EQU
		INCLUDE COMMON.EQU
		INCLUDE 8042.EQU
		INCLUDE 8254.EQU
		INCLUDE 8259.EQU
		INCLUDE 8237.EQU
		INCLUDE 82077.EQU
		INCLUDE MATHCOP.EQU
		INCLUDE port61.EQU
		INCLUDE akbrd.EQU
		INCLUDE adisk.EQU
		INCLUDE cpu.EQU
		include	BtRomSeg.equ			;R90
		include	bsetup.inc			;R102

		extrn	Get_Ct:Near
		extrn	Set_Ct:Near
		extrn	Get_Set_Ct:Near
		extrn	Move_Codes:Near

Error_Flag		EQU	byte ptr [bp]
	KbdCtrl_Err	EQU	00000001b
	KeyBoard_Err	EQU	00000010b

COMPRESSED_UNKNOW_BYTE	EQU	3
SPURIOUS_INT_HDLR	EQU	IRET_VECT
BootPOST_STK		EQU	1000h
BootPOST_data		EQU	0c00h
CR			EQU	0dh
LF			EQU	0ah

GAPRINT			EQU	NOT FALSE
ORG_OFFSET		EQU	0E000h			; OFFSET OF OVERLAY

;amount of time to wait for head settle, per unit in parameter
;table = 1 ms.
WAIT_FDU_HEAD_SETTLE	EQU	33		; 1 ms in 30 micro units.
;amount of time to wait for completion interrupt from NEC.
;1.5 seconds.
WAIT_FDU_INT_LO		EQU	050000			; 1.5 secs in 30 micro units.
WAIT_FDU_INT_HI		EQU	0

;Time to wait while waiting for each byte of NEC results = .5
;seconds.  .5 seconds = 500,000 micros.  500,000/30 = 16,667.
WAIT_FDU_RESULTS_LO	EQU	16667		; .5 seconds in 30 micro units.
WAIT_FDU_RESULTS_HI	EQU	0

;amount of time to wait for motor spin up, per unit in
;parameter table = 1/8th of second.
WAIT_FDU_8THS	EQU	4167	; 125,000/30 = 1/8th second in 30 micro units.

;Time to wait in between sending each byte of command to NEC =
;.5 seconds. .5 seconds = 500,000 us.  500,000/30 = 16,667.
WAIT_FDU_SEND_LO	EQU	16667		; .5 secons in 30 us units.
WAIT_FDU_SEND_HI	EQU	0

		INCLUDE EXP.EQU                         ; some equates

UpdateCRC	macro
		push	ax
		push	bx
		push	si

		mov	si,ax
		mov	ax,word ptr ds:crc
		xor	ax,si
		and	ax,00ffh
		mov	si,ax
		shl	si,1
		mov	bx,word ptr crctable[si]
		mov	ax,word ptr ds:crc
		shr	ax,8
		xor	ax,bx
		mov	word ptr ds:crc,ax

		pop	si
		pop	bx
		pop	ax
	ENDM

;
; The following data segment for data decompression is needed in very early
; POST stage and could be discarded completely after decompression job is
; done. The segment is now hard coded as 3000h and could be relocated to
; anywhere of base memory area. The size of this segment is about 22K.
;

EXP_DATA	SEGMENT	USE16 AT 3000H

	ORG	3000H



	Header                  db      255 dup(?)
	namelen			db	? ; Note! one byte long only


	SrcSegment		dw	?
	SrcOffset		dw	?


	TgtSegment		dw	?
	TgtOffset		dw	?

	ExpSegment		dw	?
	ExpOffset		dw	?

	crctable                dw      (UCHAR_MAX+1) dup(?)
	crc                     dw      ?
	bitbuf                  dw      ?
	compsize                dd      ?
	origsize                dd      ?
	left                    dw      (2 * NC - 1) dup(?)
	right                   dw      (2 * NC - 1) dup(?)
	buf                     db      ?
	c_len                   db      NC dup(?)
	pt_len                  db      NPT dup(?)
	blocksize               dw      ?
	c_table                 dw      4096 dup(?)
	pt_table                dw      256 dup(?)

	subbitbuf               dw      ?
	bitcount                dw      ?
	buffer                  db      DICSIZ dup(?);
	headersize              db      ?
	headersum               db      ?
	file_crc                dw      ?
	temp_name               dw      ?	; store pointer to filename
	j			dw	?	; remaining bytes to copy
	temp_param		dw	?	; for storing temp parameter
	count			dw	17 dup(?)
	weight			dw	17 dup(?)
	start			dw	18 dup(?)
	vmask			dw	?
	avail			dw	?
	nchar			dw	?
	nextcode		dw	?
	jutbits			dw	?
	len			dw	?
	i			dw	?
	k			dw	?
	p			dw	?	; pointer
	s_i			dw	?	; static i

EXP_DATA	ENDS

SEG_0		SEGMENT	USE16 AT 0

		org	10h
		INCLUDE SEG_0.INC

SEG_0		ENDS

G_RAM		SEGMENT USE16 AT 0

		ORG	400H
		INCLUDE G_RAM.INC

		ORG	412h
Floppy_CMOS_Type	Label	Byte

		ORG	7C00H
BOOT		LABEL	FAR

G_RAM		ENDS

DGROUP		GROUP	FCODE
FCODE		SEGMENT	USE16 DWORD PUBLIC 'CODE'
		ASSUME	CS:DGROUP,DS:EXP_DATA

ifdef	Flash_2M_support			;R122
ifdef	Bootblock_16K_Support			;R129
		DB	0c000h dup (0ffh)	;R122
else;	Bootblock_16K_Support			;R129
		DB	0e000h dup (0ffh)	;R129
endif;	Bootblock_16K_Support			;R129
else	;Flash_2M_support			;R122
		DB	0e000h dup (0ffh)
endif	;Flash_2M_support			;R122

;R105 start
ifdef	P6_BIOS_ONLY
		org	P6_Block_Start_Seg

		include	P6UPD.INC		;R126

endif	;P6_BIOS_ONLY
;R105 end
;R90		org	0c000h
		org	Decompress_Code_Seg	;R90

		db	'= Award Decompression Bios =',0

	; subroutines

;R108A start
;!!!!!!!!!!! Don't move this section code for compatible old BIOS !!!!!!!!!!!
	Expand_To_RAM	proc	near
	;
	; Enable the shadow area we want to expand our data to,
	; copy data from temp buffer to this area according to 'origsize'
	; shadow this area then write protect this area.
	; EAX : Original (Uncompressed) file size
	; ES : Segment of Expansion area
	; DI : starting offset of Expansion area
	; DS : Segment of target buffer area
	; SI : starting offset of target buffer area
	; NOTE !!! : This could be a cross-segment far call
	;

	; Please use the parameters passed in to determine how many pages
	; of shadow memory you have to 'SHADOW'
	; This sample does not bother to check by simply using 32K of E000 segment


	; copy from buffer to shadow memory

		shr	eax,1
Expand_Loop:
		mov	cx,8000h
		cmp	eax,8000h
		jae	short @F
		mov	cx,ax
@@:
		rep	movsw
		mov	cx,ds
		add	ch,10h		;next segment
		mov	ds,cx
		mov	cx,es
		add	ch,10h		;next segment
		mov	es,cx
		sub	eax,8000h
		ja	short Expand_Loop
		ret

	Expand_To_RAM	endp
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;R108A end

	CleanUpBaseMemory	proc	near
	;
	; clean up the temp buffer we used for data storage before boot
	; clear the whole segment of 3000h where we used for data area
	; also clear the whole segment of 8000h where TgtSegment located at.
	;

		nop			;R108A !!!!! Don't move !!!!!
		mov	ax,ds
		mov	es,ax
		xor	di,di
		mov	cx,2000h
		xor	eax,eax
		rep	stosd

;R108A start
;!!!!!!!!!!! Don't move this section code for compatible old BIOS !!!!!!!!!!!
		jmp	@F
		mov	es,ax
		xor	di,di
		mov	cx,4000h
		xor	eax,eax
		rep	stosd

		cmp	dword ptr origsize,10000h ; more than 64K ?
		jbe	short @F

		mov	ax,TGT_SEGMENT	; then we need to clean up another segment
		add	ax,1000h
		mov	es,ax
		xor	di,di
		mov	cx,4000h
		xor	eax,eax
		rep	stosd
	@@:
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;R108A end

		ret

	CleanUpBaseMemory	endp


	FwriteCRC	proc	near
	;
	; Input : CX -- number of bytes to write to output file
	;

		push	ax
		push	bx
		push	dx

		push	cx

		push	es
		push	si
		mov	ax,word ptr TgtSegment
		mov	es,ax
		mov	bx,word ptr TgtOffset
		mov	si,offset buffer
	FWCRC_0:
		mov	al,ds:[si]
		mov	es:[bx],al
		inc	si
		inc	bx
		loop	short FWCRC_0
		mov	word ptr TgtOffset,bx
		or	bx,bx	; if bx is zero means we need to change segment
		jnz	short @F
		add	word ptr TgtSegment,1000h
	@@:
		pop	si
		pop	es