atbase.asm

award bios 源代码,喜欢汇编程序及想研究主板BIOS程序的人可以参考哦.我是费了老大的劲才找到的哦.

;R23;R14B		xchg	ah,al
;R23;R14B		out	23h,al
;R23;R14 - ends
;R23
;R23		call	Cpu_Init
;R23;R20 - start
;R23ifdef	MP_SUPPORT
;R23		extrn	Cpu_Apic_Init:near
;R23		call	Cpu_Apic_Init
;R23endif;	MP_SUPPORT
;R23;R20 - end
;R23
;R23		mov	si,offset IntCache_Item
;R23		call	GetItem_Cmos
;R23		or	al,al
;R23		jz	short Not_Enable_486_Cache
;R23
;R23;		mov	al,CMOS_AWARD_CACHE  NMI_OFF
;R23;		call	Get_Cmos
;R23;		test	al,SECONDARY_CACHE
;R23;		jz	short Not_Enable_486_Cache
;R23
;R23		mov	al,1			; al = cache on		;R12
;R23		call	CPU_Cache					;R12
;R23Not_Enable_486_Cache:							;R22
;R23
;R23;R05		mov	al,8fh			; cmos shutdown byte
;R23;R05		out	CMOS,al
;R23;R05		newiodelay
;R23;R05	   	in	al,CMOS+1
;R23Not_ShutDown:					;R05
;R23		pop	ax			;R05
;R23; begin -workaround 386SL
;R23; This delay loop is here to fix QAPLUS extended memory test for 386SL
;R23; This loop should be taken away once bug is solved in hardware
;R23;
;R23;Deleted IFDEF DELAY_FOR_SHUTDOWN_BYTE_READ
;R23;Deleted 		mov	cx,100
;R23;Deleted 		loop	$
;R23;Deleted ENDIF
;R23
;R23		mov	ah,al
;R23		cmp	al,9			; if 9 or 0ah don't re-init 8259s
;R23		jae	short shut_branch
;R23
;R23;
;R23;		reset 8259s after virtual shut down
;R23;
;R23
;R23int8259init:
;R23		xor	al,al
;R23		out	MATH_PORT+1,al		; reset the co-processor
;R23		mov	bx,ax			; save the shutdown code
;R23
;R23		mov	ax,cs
;R23		mov	ds,ax
;R23
;R23		mov	si,offset int_inits
;R23		mov	cx,size_int_inits
;R23
;R23int8259_lp1:
;R23		lodsw				; get the port
;R23		mov	dx,ax			; put in correct reg
;R23		lodsb				; get byte to ouput
;R23		out	dx,al
;R23		loop	short int8259_lp1
;R23
;R23		mov	ax,bx			; restore shutdown
;R23
;R23;
;R23;		reset shutdown byte
;R23;
;R23
;R23shut_branch:
;R23		mov	al,8fh			; NMI off
;R23		out	CMOS,al
;R23		newiodelay
;R23		xor	al,al
;R23		out	CMOS+1,al
;R23
;R23	;check other shut down modes
;R23
;R23		cmp	ah,9
;R23		jne	short Chk_2
;R23		jmp	Exc9hdlr
;R23
;R23chk_2:
;R23		cmp	ah,5
;R23		je	short jmp_5init		; user return from virtual mode
;R23
;R23		cmp	ah,0ah			; user return from virtual mode without 8259 init
;R23		je	short jmp_ioinit
;R23
;R23;R02 start
;R23ifdef	PM_SUPPORT
;R23		cmp	ah,RESUME_SHUTDOWN_BYTE	; user return sleep mode
;R23;R09		je	short jmp_RESUME_HANDLE
;R23		je	jmp_RESUME_HANDLE	;R09
;R23endif	;PM_SUPPORT
;R23;R02 end
;R23
;R23		cmp	ah,4			; user return from virtual w/ boot request
;R23		jne	short chk_2a
;R23
;R23;
;R23;		enable parity, nmi (mode 4)
;R23;
;R23
;R23		call	Enable_Parity		; additional code clear parity
;R23
;R23;
;R23; 		enabling nmi is a bug fix which must stay in place here...
;R23;
;R23
;R23		mov	al,0fh NMI_ON		; enable nmi
;R23		call	Get_Cmos
;R23
;R23		int	19h			; boot
;R23
;R23chk_2a:
;R23		xor	bp,bp			; memory test fail
;R23;R23 - start
;R23		call	A20_On			; turn on A20 to match
;R23						; cold boot status
;R23;R23 - end
;R23;R01 - start
;R23;
;R23; Restore CPU type from G_RAM:CPU_TYPE_FLAG for warm boot
;R23;
;R23		mov	al,0eh					;R03
;R23		call	get_cmos				;R03
;R23		test	al,CKSM_STATUS+RTC_STATUS		;R03
;R23		jz	short @F				;R03
;R23
;R23		mov	ax,G_RAM
;R23		mov	ds,ax
;R23		assume  ds:G_RAM
;R23		mov	al,CMOS_AWARD_2 NMI_OFF
;R23		mov	ah,ds:CPU_TYPE_FLAG
;R23		call	Set_Cmos
;R23
;R23		mov	al,CMOS_OVERRIDE NMI_OFF		;R04
;R23		call	get_cmos				;R04
;R23		and	al,00111111b				;R04
;R23		mov	ah,ds:CPU_CLOCK				;R04
;R23		and	ah,00000011b				;R04
;R23		shl	ah,6					;R04
;R23		or	ah,al					;R04
;R23		mov	al,CMOS_OVERRIDE NMI_OFF		;R04
;R23		call	Set_Cmos				;R04
;R23
;R23@@:								;R03
;R23;R09 - start
;R23		mov	al,CMOS_AWARD_2 NMI_OFF
;R23		call	Get_Cmos
;R23		and	al,CPU_TYPE_MASK
;R23		cmp	al,TYPE_TI486SXL2
;R23		jne	short @F
;R23
;R23		mov	dx,CPU_TI486SXL
;R23		mov	ah,dl
;R23		mov	al,CMOS_AWARD_2 NMI_OFF
;R23		Call	Set_Cmos
;R23
;R23		mov	al,OVERRIDE NMI_OFF
;R23		Call	Get_Cmos
;R23		and	al,Not Clock_Mode
;R23		mov	ah,dh
;R23		or	ah,al
;R23		mov	al,OVERRIDE NMI_OFF
;R23		Call	Set_Cmos
;R23@@:
;R23;R09 - end
;R23;R01 - end
;R23		jmp	Pup_Wait
;R23
;R23;
;R23;	clear keyboard buffer and do an end-of-interrupt (mode 5)
;R23;
;R23
;R23jmp_5init:
;R23		in	al,DATA8042		; clear keyboard
;R23		mov	al,END_OF_INT		; clear interrupts
;R23		NEWIODELAY
;R23		out	A8259,al
;R23
;R23;
;R23;	jmp dword 40:[67] (mode 5 & 10)
;R23;
;R23
;R23jmp_ioinit:					; jmp to dword at 40:67
;R23
;R23		mov	eax,cr0
;R23		or	al,10h			; enable ET bit
;R23		mov	cr0,eax
;R23
;R23		mov	ax,G_RAM
;R23		mov	ds,ax
;R23		jmp	ds:dword ptr ROM_MODULE_OFFSET
;R23
;R23;R02 start
;R23ifdef	PM_SUPPORT
;R23jmp_RESUME_HANDLE:
;R23		mov	ax,cs
;R23		mov	ss,ax
;R23		call	CT_RESUME_HANDLE
;R23endif	;PM_SUPPORT
;R23;R02 end
;R23
;R23REDO1		ENDP


		;****************************************
		;*                                      *
		;*   MANUFACTURING POST DEFAULTS        *
		;*                                      *
		;****************************************

;R18 MAN_DEFAULT_TBL	DB	0,0,0,0,0,0,0,0,0,0

;R80;[]==============================================================[]
;R80;
;R80;SETUP_STACK:
;R80;
;R80;	Reserve stack space for user-interface routines, CMOS, etc.
;R80;
;R80;
;R80;Saves:	AX,CX
;R80;
;R80;Entry: NONE
;R80;Exit:	NONE
;R80;
;R80;Notes:	1.	TOTALSTACK is defined in STACK.EQU.
;R80;
;R80;Author: Tim Lewis
;R80;Date:   04/18/90
;R80;
;R80; Name | Date	    | Description
;R80; ---------------------------------------------------------------
;R80; TIM | 18-Apr-90   | Initial revision
;R80;
;R80;[]==============================================================[]
;R80		align	4					;R25
;R80		PUBLIC	SETUP_STACK
;R80SETUP_STACK	PROC	NEAR
;R80
;R80
;R80; Begin save BP
;R80		pop	bx			; pop return address
;R80
;R80		sub	sp,DATAAREASIZE		; reserve stack size for setup
;R80
;R80		mov	bp,sp
;R80
;R80; Begin save BP
;R80		push	ds			; save BP in G_RAM:Temp_BP
;R80		push	ax
;R80		mov	ax, G_RAM
;R80		mov	ds,ax
;R80		ASSUME DS:G_RAM
;R80		mov	word ptr [Temp_BP], bp
;R80		ASSUME DS:DGROUP
;R80		pop	ax
;R80		pop	ds
;R80
;R80		push	bx			; put return address back
;R80; End save BP
;R80
;R80		ret
;R80SETUP_STACK	ENDP
;R80
		align	4					;R25
		public	Do_F000_Shadow
Do_F000_Shadow	PROC	Near
;R90 - start
		extrn	F000_Shadow_W:near	;R90A
		extrn	F000_Shadow_R:near	;R90A
		push	si
		call	F000_Shadow_W		;enable F000 shadow R/W
		mov	ax,cs
		mov	ds,ax
		mov	es,ax
		pop	si
		call	si
		call	F000_Shadow_R		;enable F000 shadow readonly
;R90 - end

;R90		push	si
;R90
;R90;Move codes from ROM to temporary area
;R90		mov	si,0f000h		;source area
;R90		extrn	TEMP_MEM:ABS
;R90		mov	di,TEMP_MEM		;destination area
;R90		mov	cx,8000h		;64k
;R90		extrn	Move_Codes:Near
;R90		call	Move_Codes
;R90
;R90		pop	si
;R26A		push	si			;R26
;R90                call    si
;R26 start
;R26A		pop	si
;R26A		cmp	si,offset SHADOW_DR
;R26A		jne	short @F
;R26A		mov	ax,g_ram
;R26A		mov	ds,ax
;R26A		assume	ds:g_ram
;R26A		test	byte ptr ds:POST_FLAG,DRIVE1_ABSENT
;R26A		jnz	short Drive1_is_absent
;R26A 		test	byte ptr FIXED_TYPE[bp],0fh
;R26A		jnz	short @F
;R26ADrive1_is_absent:
;R26A		push	es
;R26A		pop	ds
;R26A		lea	si,DGROUP:DRV0		;move DRV0 parameter to DRV1
;R26A		lea	di,DGROUP:DRV1
;R26A		mov	cx,16
;R26A		rep	movsb
;R26A		lea	di,DGROUP:DRV0		;clear DRV0 parameter
;R26A		xor	ax,ax
;R26A		mov	cx,8
;R26A		rep	stosw
;R26A@@:
;R26 end
;R90
;R90;Jump to temporay area to execute shadowing
;R90                FAR_JMP <OFFSET DGROUP:From_RAM_To_ROM>,TEMP_MEM
;R90From_RAM_To_ROM:
;R90		cli				;disable interrupt before f000 shadow disable
;R90
;R90		extrn	F000_Shadow_W:Near
;R90		call	F000_Shadow_W		;enable F000 shadow writeable
;R90		mov	si,TEMP_MEM		;source area
;R90		mov	di,0f000h		;destination area
;R90		mov	cx,8000h		;64k
;R90		call	Move_Codes
;R90		extrn	F000_Shadow_R:Near
;R90		call	F000_Shadow_R		;enable F000 shadow readonly
;R90
;R90		sti				;enable interrupt after f000 shadow enable
;R90
;R90                FAR_JMP <OFFSET DGROUP:Return_From_RAM>,0F000H
;R90Return_From_RAM:
		ret
Do_F000_Shadow	ENDP

;[]==============================================================[]
;
;PUP_WAIT:
;
;	Disable the cache and then fall into POST
;
;Saves:	NONE
;
;Entry:	BP	POST code to display
;
;Exit:	NEVER
;
;Author: Award
;Date:   04/18/90
;
; Name | Date	    | Description
; ---------------------------------------------------------------
; TIM  | 23-Aug-90  | Now only do 486 cache turn off here.
; TIM  | 18-Apr-90  | Update to 4.0
;
;[]==============================================================[]

		align	4					;R25
		PUBLIC	PUP_WAIT
PUP_WAIT	PROC	NEAR

		mov	ax,cs
		mov	ss,ax			; ss = cs

;Deleted ;R14 - start
;Deleted ifdef	WAIT_CHIPSET_TO_COME_UP
;Deleted 		xor	cx,cx
;Deleted 		loop	$
;Deleted endif;	WAIT_CHIPSET_TO_COME_UP
;Deleted ;R14 - end

;Begin 486 only cache off
;
;	Disable the 486 internal cache.
;

;Program chipset registers before POST
		POST_CODE 0c0h
		mov	sp,0F80Bh
		extrn	Ct_Very_Early_Init:Near
		jmp	Ct_Very_Early_Init

;R80		public	PUP_WAIT1
;R80PUP_WAIT1:
;R80		extrn	Power_On_Delay:word
;R80		mov	cx,cs:[Power_On_Delay]
;R80		jcxz	short @F
;R80Wait_Chipset:
;R80		NEWIODELAY
;R80		loop	short Wait_Chipset
;R80@@:
;R80		mov	ax,BIOS_STK
;R80		mov	ss,ax
;R80		mov	sp,offset POSTSTK_TOP
;R80
;R80		call	Setup_Stack
;R80
PUP_WAIT	ENDP
;R80
;R80;[]==============================================================[]
;R80;
;R80; POST_1s:
;R80;
;R80;	Test processor status flags. If bad, halt system.
;R80;
;R80;Saves:	NONE + NO STACK
;R80;
;R80;Entry: NONE
;R80;Exit:	NONE
;R80;
;R80;Author: Award
;R80;Date:   04/18/90
;R80;
;R80; Name | Date	    | Description
;R80; ---------------------------------------------------------------
;R80; TIM | 18-Apr-90   | Update to 4.0
;R80;
;R80;[]==============================================================[]
;R80
;R80		PUBLIC	POST_1S
;R80POST_1S		PROC	NEAR
;R80
;R80;	prevent hang on post 4
;R80
;R18 		POST_CODE 1
;R18 		stc				; check carry
;R18 		jnc	short post_1_fail
;R18 		clc
;R18 		jc	short post_1_fail
;R18
;R18 		xor	ax,ax			; check zero clear
;R18 		jnz	short post_1_fail
;R18 		jo	short post_1_fail	; overflow clear
;R18 		js	short post_1_fail	; sign clear
;R18
;R18 		or	ax,-1
;R18 		jz	short post_1_fail	; not zero set
;R18 		jns	short post_1_fail	; sign set
;R18
;R18 		mov	ax,7fffh
;R18 		add	ax,7fffh		; overflow set
;R18 		jno	short post_1_fail
;R18
;R18 		jmp	short Post_2s
;R18 post_1_fail:
;R18 		jmp	haltsystem
;R80POST_1S		ENDP
;R80
;R80;[]==============================================================[]
;R80;
;R80; POST_2S:
;R80;
;R80;	Test processor registers. If bad, halt system. Test all
;R80;	registers except CS with patterns 0ffffh, 0000h, 5555h
;R80;	and 0aaaah.
;R80;
;R80;Saves:	NONE + NO STACK
;R80;
;R80;Entry: NONE
;R80;Exit:	NONE
;R80;
;R80;Author: Award
;R80;Date:   04/18/90
;R80;
;R80; Name | Date	    | Description
;R80; ---------------------------------------------------------------
;R80; TIM | 18-Apr-90   | Update to 4.0, add 386/486 register tests.