📄 hpi_epp.vhd
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---HPI与EPP接口转换模块的设计
---本设计以EPP的时序为基础，要求以host能够通过HPI接口可访问DSP的存储空间
--程序名称 ：HPI_EPP
--编译环境 ：ISE5.2
--程序版本 ：1.0
--主体设计者 : 吴庆洪
--程序编制调试：李思伟
--设计时间 : 2005.4
-------------------------------------------------------------------------------
--entity:count16
--founction:产生16进制的进位脉冲，作为HPI接口控制信号。
--signal:nAstrb,nDstrb,byteflage,HHWIL,HCNTL0,HCNTL1;
--实体count16作为epp_interface的子器件。
--time: 2005.4
--chang time: 2005.4.1
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity count16 is
port(
nAstrb: in STD_LOGIC; --地址选通信号，作为计数器的清零信号
nDstrb: in STD_LOGIC; --数据选通信号，作为计数器的计数脉冲
Q0: out STD_LOGIC;
Q1: out STD_LOGIC;
Q2: out STD_LOGIC;
Q3: out STD_LOGIC
);
end count16;
architecture count16_arch of count16 is
signal cnt :std_logic_vector(3 downto 0);
signal hostdata:std_logic_vector(15 downto 0);
begin
COUNT:process(nAstrb,nDstrb)
begin
if(nAstrb='0') then
cnt<="0000";
elsif(nDstrb'event and nDstrb='0')then
if(cnt="1011")then
cnt<="1000";
else
cnt<=cnt+'1';
end if;
Q1<=cnt(1);
Q2<=cnt(2);
Q3<=cnt(3);
Q0<=cnt(0);--after 100ns; --用于锁存从host输出的八位数据，延时使Q0的边沿在数据有效时发生
end if;
end process COUNT;
-- <<enter your statements here>>
end count16_arch;
-------------------------------------------------------------------------------------------------------
--entity:latch
--founction:HPI口写DSP控制寄存器时，nWrite='0'时，用于锁存低8位的PD信号，在Q0的上升沿送给HD（7 DOWNTO 0）。
--signal:PD(7downto 0),HD(7 downto 0),Q0,nWrite;
--实体latch作为epp_interface的子器件。
--time:2005.4
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity latch is
port(
d: in STD_LOGIC_VECTOR (7 downto 0);
q: out STD_LOGIC_VECTOR (15 downto 0);
clk: in STD_LOGIC;
Q0: in STD_LOGIC;
oe: in STD_LOGIC
);
end latch;
architecture latch_arch of latch is
signal qint:std_logic_vector(7 downto 0);
begin
process(clk,d,oe)
begin
if(oe='0')then
if(clk'event and clk='0')then --clk的上升沿锁存低八位数据
qint<=d;
end if;
else
qint<="ZZZZZZZZ";
end if;
if(oe='0'and Q0='1')then
q(7 downto 0)<=qint;
elsif(oe='0'and Q0='0')then
q(15 downto 8)<=qint;
else
q<="ZZZZZZZZZZZZZZZZ";
end if;
end process;
end latch_arch;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity read is
port(
PD: out STD_LOGIC_VECTOR (7 downto 0);
HD: in STD_LOGIC_VECTOR (15 downto 0);
sclk: in STD_LOGIC;
Q0: in std_logic;
nWrite: in STD_LOGIC;
nDstrb: in std_logic
);
end read;
architecture read_arch of read is
signal bufferdata:std_logic_vector(15 downto 0);
begin
process(nWrite,HD,nDstrb,Q0,sclk)
begin
if(nWrite='1')then
if(sclk'event and sclk='1')then --CLK的上升沿锁存HPI口数据
bufferdata<=HD;
end if;
if((Q0 and (not nDstrb))='1')then
PD<=bufferdata(7 downto 0);
elsif((Q0 or nDstrb)='0')then
PD<=bufferdata(15 downto 8);
else
PD<="ZZZZZZZZ";
end if;
end if;
end process;
end read_arch;
---------------------------------------------------------------------------------------------------
--entity: HPI_EPP
--founction:HPI与EPP接口转换的主控函数。
--signal:PD(7downto 0),HD(7 downto 0),nWrite,nAstrb,nDstrb,byteflage,HHWIL,HCNTL0,HCNTL1,HCS;
--time:2005.4
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity HPI_EPP is
port (
nWrite: in STD_LOGIC; --EPP读写控制信号，‘0’--写；‘1’--读
nAstrb: in STD_LOGIC; --EPP地址选通信号，作为计数器的清零信号
nDstrb: in STD_LOGIC; --EPP的数据选通信号
byteflage: out STD_LOGIC; --数据读写高低字节的标志‘1’低，‘0’高
HHWIL: out STD_LOGIC; --HPI读写高低半字的控制信号，‘0’低，‘1’高
HCNTL0: out STD_LOGIC; --访问HPI内部寄存器HPIC、HPIA、HPID的控制信号
HCNTL1: out STD_LOGIC; --以及访问HPID的方式
HPI_RW: out STD_LOGIC; --HPI读写控制信号
PD: inout STD_LOGIC_VECTOR(7 downto 0); --EPP数据地址总线
HD: inout STD_LOGIC_VECTOR(15 downto 0);--HPI数据总线
HCS: out STD_LOGIC --HPI选通信号，下降沿锁存HPI的控制信号
);
end HPI_EPP;
architecture HPI_EPP_arch of HPI_EPP is
component count16 is --元件声明
port(
nAstrb: in STD_LOGIC;
nDstrb: in STD_LOGIC;
Q0: out STD_LOGIC;
Q1: out STD_LOGIC;
Q2: out STD_LOGIC;
Q3: out STD_LOGIC
);
end component;
component latch is
port(
d: in STD_LOGIC_VECTOR (7 downto 0);
q: out STD_LOGIC_VECTOR (15 downto 0);
clk: in STD_LOGIC;
Q0: in std_logic;
oe: in STD_LOGIC
);
end component;
component read is
port(
PD: out STD_LOGIC_VECTOR (7 downto 0);
HD: in STD_LOGIC_VECTOR (15 downto 0);
sclk: in STD_LOGIC;
Q0: in std_logic;
nWrite: in STD_LOGIC;
nDstrb: in std_logic
);
end component;
signal Q0,Q1,Q2,Q3:STD_LOGIC;
signal rwselect:std_logic;
signal portdata:std_logic_vector(7 downto 0);
signal sclk:std_logic;
-- signal bufferdata:std_logic_vector(15 downto 0);
begin
byteflage<=Q0;
HPI_RW<=nWrite;
HHWIL<=Q1;
HCNTL0<=Q2;
HCNTL1<=Q3;
HCS<=(not Q0) or nDstrb;
sclk<=nDstrb and Q0 after 200ns;
process(nAstrb)
begin
if(nAstrb='0')then
HD<="ZZZZZZZZZZZZZZZZ";
end if;
end process;
CNT1:COUNT16 PORT MAP(nAstrb,nDstrb,Q0,Q1,Q2,Q3);
Write_data:latch port map(PD,HD(15 downto 0),nDstrb,Q0,nWrite);
read_data:read port map(PD,HD,sclk,Q0,nWrite,nDstrb);
-- process(nWrite,HD,nDstrb,Q0,sclk)
-- begin
-- if(nWrite='1')then
-- if(sclk'event and sclk='1')then --CLK的上升沿锁存HPI口数据
-- bufferdata<=HD;
-- end if;
-- if((Q0 and (not nDstrb))='1')then
-- PD<=bufferdata(7 downto 0);
-- elsif((Q0 or nDstrb)='0')then
-- PD<=bufferdata(15 downto 8);
-- else
-- PD<="ZZZZZZZZ";
-- end if;
-- end if;
-- end process;
end HPI_EPP_arch;
------------------------------------------------------------------------------------------
---程序结束！
---程序结束日期：2005.4.6
---程序调试日期：2005.4.11
---程序基本功能实现，能够通过HPI实现对DSP存储空间的访问－读写。
--------------------------------------------------------------------------------------------
---程序功能完全实现日期：2005.4.21
---程序的稳定性有待进一步的验证，其他功能要求在上位机由C++Builder实现。
---程序的完美性要求对VHDL语言和CPLD设计有更深的理解，设计水平要求再上新的台阶！！
---程序的完成有赖于吴老师总的指导思想！
---程序补充时间
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