📄 epp_interface.vhd
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---HPI与EPP接口转换模块的设计
---本设计以EPP的时序为基础，要求以host能够通过HPI接口可访问DSP的存储空间
--chang time:2005.4.21
--chang part: entity:read
---HPI与EPP接口转换模块的设计
---本设计以EPP的时序为基础，要求以host能够通过HPI接口可访问DSP的存储空间
--程序名称 ：HPI_EPP
--编译环境 ：ISE5.2
--程序版本 ：1.0
--主体设计者 : 吴庆洪
--程序编制调试：李思伟
--设计时间 :2005.4
-------------------------------------------------------------------------------
--entity:count16
--founction:产生16进制的进位脉冲，作为HPI接口控制信号。
--signal:nAstrb,nDstrb,byteflage,HHWIL,HCNTL0,HCNTL1;
--实体count16作为epp_interface的子器件。
--time:2005.4
--chang time:2005.4.1
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity count16 is
port (
nAstrb: in STD_LOGIC; --地址选通信号，作为计数器的清零信号
nDstrb: in STD_LOGIC; --数据选通信号，作为计数器的计数脉冲
Q0: out STD_LOGIC;
Q1: out STD_LOGIC;
Q2: out STD_LOGIC;
Q3: out STD_LOGIC
);
end count16;
architecture count16_arch of count16 is
signal cnt :std_logic_vector(3 downto 0);
signal hostdata:std_logic_vector(15 downto 0);
begin
COUNT:process (nAstrb,nDstrb)
begin
if(nAstrb='0') then
cnt<="0000";
elsif(nDstrb'event and nDstrb='0') then
if(cnt="1011")then
cnt<="1000";
else
cnt<=cnt+'1';
end if;
Q1<=cnt(1);
Q2<=cnt(2);
Q3<=cnt(3);
Q0<=cnt(0);--after 100ns; --用于锁存从host输出的八位数据，延时使Q0的边沿在数据有效时发生
end if;
end process COUNT;
-- <<enter your statements here>>
end count16_arch;
-------------------------------------------------------------------------------------------------------
--entity:latchl
--founction:HPI口写DSP控制寄存器时，nWrite='0'时，用于锁存低8位的PD信号，在Q0的上升沿送给HD（7 DOWNTO 0）。
--signal:PD(7downto 0),HD(7 downto 0),Q0,nWrite;
--实体latchl作为epp_interface的子器件。
--time:2005.4
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity latchl is
port (
d: in STD_LOGIC_VECTOR (7 downto 0);
q: out STD_LOGIC_VECTOR (7 downto 0);
clk: in STD_LOGIC;
oe: in STD_LOGIC
);
end latchl;
architecture latchl_arch of latchl is
signal qint:std_logic_vector(7 downto 0);
begin
process(clk,d,oe)
begin
if(oe='0')then
if(clk'event and clk='1')then --clk的上升沿锁存低八位数据
qint(7 downto 0)<=d;
end if;
else
qint<="ZZZZZZZZ";
end if;
end process;
q<=qint when (oe='0') --HPI写时序，将数据送入HD0-HD7
else "ZZZZZZZZ";
-- <<enter your statements here>>
end latchl_arch;
-------------------------------------------------------------------------------------------------------
--entity:latchh
--founction:HPI口写DSP控制寄存器时，nWrite='0'时，用于锁存低8位的PD信号，在Q0的下降沿送给HD（15 downto 8）。
--signal:PD(7downto 0),HD(15 downto 8),Q0,nWrite;
--实体latchh作为epp_interface的子器件。
--time:2005.4
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity latchh is
port (
d: in STD_LOGIC_VECTOR (7 downto 0);
q: out STD_LOGIC_VECTOR (7 downto 0);
clk: in STD_LOGIC;
oe: in STD_LOGIC
);
end latchh;
architecture latchh_arch of latchh is
signal qint:std_logic_vector(7 downto 0);
begin
process(clk,d)
begin
if(oe='0')then
if(clk'event and clk='0')then --clk的下降沿锁存高八位数据
qint<=d;
end if;
else
qint<="ZZZZZZZZ";
end if;
end process;
q<=qint when (oe='0') --HPI写时序，将数据送入HD8-HD15
else "ZZZZZZZZ";
-- <<enter your statements here>>
end latchh_arch;
-----------------------------------------------------------------------------------------------------
--entity:readbuffer
--founction:HPI口读DSPMemory时，nWrite='1'时用于缓冲HD的信号，在Q0的上升沿送HD（7 DOWNTO 0）给PD，Q0的下降沿送HD（15 DOWNTO 8）给PD。
--signal:PD(7downto 0),HD(7 downto 0),Q0,nWrite;
--实体latchl作为epp_interface的子器件。
--time:2005.4
------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity read is
port (
datain: in STD_LOGIC_VECTOR (15 downto 0);
dataout: out STD_LOGIC_VECTOR (7 downto 0);
oe: in STD_LOGIC;
clk: in STD_LOGIC;
Q0: in std_logic
);
end read;
architecture read_arch of read is
signal bufferdata:std_logic_vector(15 downto 0);
--signal flage:std_logic;
begin
process(oe,clk,datain,Q0)
begin
if(oe='1'and Q0='1')then --读允许且HPI读时序时，HPI数据送入CPLD（）
if(clk'event and clk='1')then --CLK的上升沿锁存HPI口数据
bufferdata<=datain;
--flage<=not flage;
end if;
--else
-- bufferdata<=bufferdata; --否则缓存维持上次读取的数据
--flage<='Z';
end if;
end process;
dataout<=bufferdata(7 downto 0) when(Q0='1'and oe='1') --第一个CLK的上升沿，读取低八位
else bufferdata(15 downto 8)when(Q0='0'and oe='1') --第二个CLK的下降沿，读取高八位
else "ZZZZZZZZ";
-- <<enter your statements here>>
end read_arch;
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
---read and write control
--读写信号锁存
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity rwcontrol is
port (
clk: in STD_LOGIC;
nWrite: in STD_LOGIC;
rwselect: out STD_LOGIC
);
end rwcontrol;
architecture rwcontrol_arch of rwcontrol is
begin
process(clk)
begin
if(clk'event and clk='0')then
rwselect<=nWrite;
end if;
end process;
-- <<enter your statements here>>
end rwcontrol_arch;
---------------------------------------------------------------------------------------------------
--entity: HPI_EPP
--founction:HPI与EPP接口转换的主控函数。
--signal:PD(7downto 0),HD(7 downto 0),nWrite,nAstrb,nDstrb,byteflage,HHWIL,HCNTL0,HCNTL1,HCS;
--
--time:2005.4
--
--
--
--
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity HPI_EPP is
port (
nWrite: in STD_LOGIC; --EPP读写控制信号，‘0’--写；‘1’--读
nAstrb: in STD_LOGIC; --EPP地址选通信号，作为计数器的清零信号
nDstrb: in STD_LOGIC; --EPP的数据选通信号
byteflage: out STD_LOGIC; --数据读写高低字节的标志‘1’低，‘0’高
HHWIL: out STD_LOGIC; --HPI读写高低半字的控制信号，‘0’低，‘1’高
HCNTL0: out STD_LOGIC; --访问HPI内部寄存器HPIC、HPIA、HPID的控制信号
HCNTL1: out STD_LOGIC; --以及访问HPID的方式
HPI_RW: out STD_LOGIC; --HPI读写控制信号
PD:inout STD_LOGIC_VECTOR(7 downto 0); --EPP数据地址总线
HD:inout STD_LOGIC_VECTOR(15 downto 0); --HPI数据总线
datatest:out std_logic_vector(15 downto 0);
sclk:inout std_logic;
HCS: out STD_LOGIC --HPI选通信号，下降沿锁存HPI的控制信号
);
end HPI_EPP;
architecture HPI_EPP_arch of HPI_EPP is
component count16 is --元件声明
port (
nAstrb: in STD_LOGIC;
nDstrb: in STD_LOGIC;
Q0: out STD_LOGIC;
Q1: out STD_LOGIC;
Q2: out STD_LOGIC;
Q3: out STD_LOGIC
);
end component;
component latchl is
port (
d: in STD_LOGIC_VECTOR (7 downto 0);
q: out STD_LOGIC_VECTOR (7 downto 0);
clk: in STD_LOGIC;
oe: in STD_LOGIC
);
end component;
component latchh is
port (
d: in STD_LOGIC_VECTOR (7 downto 0);
q: out STD_LOGIC_VECTOR (7 downto 0);
clk: in STD_LOGIC;
oe: in STD_LOGIC
);
end component;
component read is
port (
datain: in STD_LOGIC_VECTOR (15 downto 0);
dataout: out STD_LOGIC_VECTOR (7 downto 0);
oe:in std_logic;
clk:in std_logic;
Q0:in std_logic
);
end component;
component rwcontrol is
port (
clk: in STD_LOGIC;
nwrite:in std_logic;
rwselect: out STD_LOGIC
);
end component ;
signal Q0,Q1,Q2,Q3:STD_LOGIC;
signal rwselect:std_logic;
signal portdata:std_logic_vector(7 downto 0);
-- signal sclk:std_logic;
begin
byteflage<=Q0;
HPI_RW<=nWrite;
HHWIL<=Q1;
HCNTL0<=Q2;
HCNTL1<=Q3;
HCS<=(not Q0) or nDstrb;
process(nDstrb)
begin
if(sclk'event and sclk='1')then
--sclk<=not sclk;
datatest<=HD;
end if;
end process;
sclk<=nDstrb and Q0;-- after 100ns;
readwrite:rwcontrol port map(nDstrb,nWrite,rwselect);
CNT1:COUNT16 PORT MAP(nAstrb,nDstrb,Q0,Q1,Q2,Q3);
latch1:latchh port map(PD,HD(15 downto 8),Q0,rwselect);
latch0:latchl port map(PD,HD(7 downto 0),Q0,rwselect);
-- B1:block (nWrite='1')
-- begin
bufferread:read port map(HD(15 downto 0),PD,nWrite,sclk,Q0);
-- end block B1;
end HPI_EPP_arch;
------------------------------------------------------------------------------------------
---程序结束！
---程序结束日期：2005.4.6
---程序调试完成日期：2005.4.13
---程序基本功能实现，能够通过HPI实现对DSP存储空间的访问－读写。
---存在缺点：1、功能太简单，一次仅仅能够对单独存储空间的访问。－－上位机的工作，已解决！
--- 2、读取数据时，上位机没能指定读取地址。且读出的数据只能半位有效。
--- 3、要实现对连续地址的连续访问需要改变控制信号：HCNTL0,HCNTL1 －－问题已解决
--- 在访问HPIC和HPIA后，HCNTL0和HCNTL1要固定在01上，使主机能够
--- 实现对HPID的地址自增方式的访问－－－问题已解决
--- 4、程序运行有待于继续检测，考察其稳定性
------------------------------------------------------------------------------------------
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