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   NET name 'PD<4>'. NET is 'pd<4>'.
INFO:NgdBuild:740 - Line 310 in 'myepp.ucf': Found case insensitive match for
   NET name 'PD<5>'. NET is 'pd<5>'.
INFO:NgdBuild:740 - Line 311 in 'myepp.ucf': Found case insensitive match for
   NET name 'PD<6>'. NET is 'pd<6>'.
INFO:NgdBuild:740 - Line 312 in 'myepp.ucf': Found case insensitive match for
   NET name 'PD<7>'. NET is 'pd<7>'.
INFO:NgdBuild:740 - Line 313 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<0>'. NET is 'hd<0>'.
INFO:NgdBuild:740 - Line 314 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<1>'. NET is 'hd<1>'.
INFO:NgdBuild:740 - Line 315 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<2>'. NET is 'hd<2>'.
INFO:NgdBuild:740 - Line 316 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<3>'. NET is 'hd<3>'.
INFO:NgdBuild:740 - Line 317 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<4>'. NET is 'hd<4>'.
INFO:NgdBuild:740 - Line 318 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<5>'. NET is 'hd<5>'.
INFO:NgdBuild:740 - Line 319 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<6>'. NET is 'hd<6>'.
INFO:NgdBuild:740 - Line 320 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<7>'. NET is 'hd<7>'.
INFO:NgdBuild:740 - Line 321 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<8>'. NET is 'hd<8>'.
INFO:NgdBuild:740 - Line 322 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<9>'. NET is 'hd<9>'.
INFO:NgdBuild:740 - Line 323 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<10>'. NET is 'hd<10>'.
INFO:NgdBuild:740 - Line 324 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<11>'. NET is 'hd<11>'.
INFO:NgdBuild:740 - Line 325 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<12>'. NET is 'hd<12>'.
INFO:NgdBuild:740 - Line 326 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<13>'. NET is 'hd<13>'.
INFO:NgdBuild:740 - Line 327 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<14>'. NET is 'hd<14>'.
INFO:NgdBuild:740 - Line 328 in 'myepp.ucf': Found case insensitive match for
   NET name 'HD<15>'. NET is 'hd<15>'.
INFO:NgdBuild:740 - Line 329 in 'myepp.ucf': Found case insensitive match for
   NET name 'HHWIL'. NET is 'hhwil'.
INFO:NgdBuild:740 - Line 330 in 'myepp.ucf': Found case insensitive match for
   NET name 'HCNTL0'. NET is 'hcntl0'.
INFO:NgdBuild:740 - Line 331 in 'myepp.ucf': Found case insensitive match for
   NET name 'HCNTL1'. NET is 'hcntl1'.
INFO:NgdBuild:740 - Line 332 in 'myepp.ucf': Found case insensitive match for
   NET name 'HCS'. NET is 'hcs'.
INFO:NgdBuild:740 - Line 333 in 'myepp.ucf': Found case insensitive match for
   NET name 'HDS'. NET is 'hds'.
INFO:NgdBuild:740 - Line 334 in 'myepp.ucf': Found case insensitive match for
   NET name 'HPI_RW'. NET is 'hpi_rw'.

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "hpi_epp.ngd" ...

Writing NGDBUILD log file "hpi_epp.bld"...

NGDBUILD done.

Completed process "Translate".



Started process "Fit".

Release 5.2i - CPLD Optimizer/Partitioner F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Considering device XC95144XL-TQ100.
Flattening design..
Timing optimization......................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 68 equations into 8 function blocks......................

Design hpi_epp has been optimized and fit into device XC95144XL-10-TQ100.

Completed process "Fit".


Started process "Generate Timing".

Release 5.2i - Timing Report Generator F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Path tracing ......
The number of paths traced: 357.

Generating performance summary ...
Generating Pad-to-Pad delay section ...
Generating Clock-to-Output-Pad delay section ...
Generating Setup-To-Clock-At-Pad delay section ...
Generating Register-To-Register delay section ...
     Cycle time table for clock q0.Q ...
     Cycle time table for clock ndstrb ...

hpi_epp.tim has been created.

Generating Stamp model files hpi_epp.mod, hpi_epp.data ...
hpi_epp.mod has been created.
hpi_epp.data has been created.

Completed process "Generate Timing".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Generate Programming File".

Release 5.2i - Programming File Generator F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    hpi_epp.vhd
Scanning    hpi_epp.vhd
Writing hpi_epp.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/程序/myepp4_21/hpi_epp.vhd in Library work.
Entity <count16> (Architecture <count16_arch>) compiled.
Entity <latchl> (Architecture <latchl_arch>) compiled.
Entity <latchh> (Architecture <latchh_arch>) compiled.
Entity <read> (Architecture <read_arch>) compiled.
Entity <rwcontrol> (Architecture <rwcontrol_arch>) compiled.
Entity <hpi_epp> (Architecture <hpi_epp_arch>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <hpi_epp> (Architecture <hpi_epp_arch>).
INFO:Xst:1304 - Contents of register <hd> in unit <hpi_epp> never changes during circuit operation. The register is replaced by logic.
Entity <hpi_epp> analyzed. Unit <hpi_epp> generated.

Analyzing Entity <rwcontrol> (Architecture <rwcontrol_arch>).
Entity <rwcontrol> analyzed. Unit <rwcontrol> generated.

Analyzing Entity <count16> (Architecture <count16_arch>).
Entity <count16> analyzed. Unit <count16> generated.

Analyzing Entity <latchh> (Architecture <latchh_arch>).
WARNING:Xst:819 - E:/程序/myepp4_21/hpi_epp.vhd line 112: The following signals are missing in the process sensitivity list:
   oe.
Entity <latchh> analyzed. Unit <latchh> generated.

Analyzing Entity <latchl> (Architecture <latchl_arch>).
Entity <latchl> analyzed. Unit <latchl> generated.

Analyzing Entity <read> (Architecture <read_arch>).
WARNING:Xst:819 - E:/程序/myepp4_21/hpi_epp.vhd line 151: The following signals are missing in the process sensitivity list:
   nastrb.
Entity <read> analyzed. Unit <read> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <read>.
    Related source file is E:/程序/myepp4_21/hpi_epp.vhd.
    Found 16-bit tristate buffer for signal <dataout>.
    Found 16-bit register for signal <Mtridata_dataout> created at line 158.
WARNING:Xst:647 - Input <q0> is never used.
WARNING:Xst:647 - Input <oe> is never used.
    Summary:
	inferred  16 Tristate(s).
Unit <read> synthesized.


Synthesizing Unit <latchl>.
    Related source file is E:/程序/myepp4_21/hpi_epp.vhd.
    Found 8-bit tristate buffer for signal <q>.
    Found 8-bit register for signal <Mtridata_qint> created at line 80.
    Found 8-bit tristate buffer for signal <qint>.
    Summary:
	inferred  16 Tristate(s).
Unit <latchl> synthesized.


Synthesizing Unit <latchh>.
    Related source file is E:/程序/myepp4_21/hpi_epp.vhd.
    Found 8-bit tristate buffer for signal <q>.
    Found 8-bit register for signal <Mtridata_qint> created at line 116.
    Found 8-bit tristate buffer for signal <qint>.
    Summary:
	inferred  16 Tristate(s).
Unit <latchh> synthesized.


Synthesizing Unit <count16>.
    Related source file is E:/程序/myepp4_21/hpi_epp.vhd.
    Found 1-bit register for signal <q0>.
    Found 1-bit register for signal <q1>.
    Found 1-bit register for signal <q2>.
    Found 1-bit register for signal <q3>.
    Found 4-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   4 D-type flip-flop(s).
Unit <count16> synthesized.


Synthesizing Unit <rwcontrol>.
    Related source file is E:/程序/myepp4_21/hpi_epp.vhd.
    Found 1-bit register for signal <rwselect>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <rwcontrol> synthesized.


Synthesizing Unit <hpi_epp>.
    Related source file is E:/程序/myepp4_21/hpi_epp.vhd.
    Found 8-bit tristate buffer for signal <pd>.
    Found 16-bit tristate buffer for signal <hd>.
    Found 8 1-bit 2-to-1 multiplexers.
WARNING:Xst:1306 - Output <hds> is never assigned.
    Summary:
	inferred  24 Tristate(s).
Unit <hpi_epp> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 8
  16-bit register                  : 1
  8-bit register                   : 2
  1-bit register                   : 5
# Counters                         : 1
  4-bit up counter                 : 1
# Multiplexers                     : 1
  2-to-1 multiplexer               : 1
# Tristates                        : 7
  16-bit tristate buffer           : 2
  8-bit tristate buffer            : 5

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/xilinx/xc9500xl/data/lib.xst" Consulted
Library "C:/xilinx/data/librtl.xst" Consulted
WARNING:Xst:1348 - Unit latchl is merged (output interface has tristates)
WARNING:Xst:1348 - Unit latchh is merged (output interface has tristates)
WARNING:Xst:1348 - Unit read is merged (output interface has tristates)

Optimizing unit <hpi_epp> ...
  implementation constraint: iob	 : bufferread_Mtridata_dataout<7>
  implementation constraint: KEEP	 : bufferread_Mtridata_dataout<7>
  implementation constraint: iob	 : latch1_Mtridata_qint<7>
  implementation constraint: KEEP	 : latch1_Mtridata_qint<7>
  implementation constraint: iob	 : latch1_Mtridata_qint<6>
  implementation constraint: KEEP	 : latch1_Mtridata_qint<6>
  implementation constraint: iob	 : latch1_Mtridata_qint<5>
  implementation constraint: KEEP	 : latch1_Mtridata_qint<5>
  implementation constraint: iob	 : latch1_Mtridata_qint<4>
  implementation constraint: KEEP	 : latch1_Mtridata_qint<4>
  implementation constraint: iob	 : latch1_Mtridata_qint<3>
  implementation constraint: KEEP	 : latch1_Mtridata_qint<3>
  implementation constraint: iob	 : latch1_Mtridata_qint<2>
  implementation constraint: KEEP	 : latch1_Mtridata_qint<2>