📄 hpi_epp.rpt
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Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 17/37
Number of signals used by logic mapping into function block: 17
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 35 I/O
(unused) 0 0 0 5 FB5_3 (b)
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 36 I/O
read_data_mtridata_pd<6>/read_data_mtridata_pd<6>_SETF
2 0 0 3 FB5_6 STD 37 I/O (b)
read_data_mtridata_pd<5>/read_data_mtridata_pd<5>_SETF
2 0 0 3 FB5_7 STD (b) (b)
cnt1/cnt<0> 2 0 0 3 FB5_8 STD 39 I/O (b)
read_data_bufferdata<15>
3 0 0 2 FB5_9 STD 40 I/O (b)
read_data_bufferdata<14>
3 0 0 2 FB5_10 STD (b) (b)
read_data_bufferdata<13>
3 0 0 2 FB5_11 STD 41 I/O (b)
byteflage 3 0 0 2 FB5_12 STD 42 I/O O
read_data_bufferdata<12>
3 0 0 2 FB5_13 STD (b) (b)
read_data_bufferdata<11>
3 0 0 2 FB5_14 STD 43 I/O (b)
cnt1/cnt<3> 3 0 0 2 FB5_15 STD 46 I/O (b)
cnt1/cnt<1> 3 0 0 2 FB5_16 STD (b) (b)
hpi_rw 1 0 0 4 FB5_17 STD 49 I/O O
cnt1/cnt<2> 4 0 0 1 FB5_18 STD (b) (b)
Signals Used by Logic in Function Block
1: byteflage 7: hd<12>.PIN 13: nwrite
2: cnt1/cnt<0> 8: hd<13>.PIN 14: read_data_bufferdata<13>
3: cnt1/cnt<1> 9: hd<14>.PIN 15: read_data_bufferdata<14>
4: cnt1/cnt<2> 10: hd<15>.PIN 16: read_data_bufferdata<5>
5: cnt1/cnt<3> 11: nastrb 17: read_data_bufferdata<6>
6: hd<11>.PIN 12: ndstrb
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
read_data_mtridata_pd<6>/read_data_mtridata_pd<6>_SETF
X..........XX.X.X....................... 5 5
read_data_mtridata_pd<5>/read_data_mtridata_pd<5>_SETF
X..........XXX.X........................ 5 5
cnt1/cnt<0> ..........XX............................ 2 2
read_data_bufferdata<15>
X........X.XX........................... 4 4
read_data_bufferdata<14>
X.......X..XX........................... 4 4
read_data_bufferdata<13>
X......X...XX........................... 4 4
byteflage .X........XX............................ 3 3
read_data_bufferdata<12>
X.....X....XX........................... 4 4
read_data_bufferdata<11>
X....X.....XX........................... 4 4
cnt1/cnt<3> .XXX......XX............................ 5 5
cnt1/cnt<1> .X........XX............................ 3 3
hpi_rw ............X........................... 1 1
cnt1/cnt<2> .XXXX.....XX............................ 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 74 I/O
(unused) 0 0 0 5 FB6_3 (b)
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 76 I/O
(unused) 0 0 0 5 FB6_6 77 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 78 I/O
(unused) 0 0 0 5 FB6_9 79 I/O
(unused) 0 0 0 5 FB6_10 (b)
(unused) 0 0 0 5 FB6_11 80 I/O
(unused) 0 0 0 5 FB6_12 81 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 82 I/O
(unused) 0 0 0 5 FB6_15 85 I/O
(unused) 0 0 0 5 FB6_16 (b)
(unused) 0 0 0 5 FB6_17 86 I/O
(unused) 0 0 0 5 FB6_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 20/34
Number of signals used by logic mapping into function block: 20
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB7_1 (b)
hhwil 3 0 0 2 FB7_2 STD 50 I/O O
(unused) 0 0 0 5 FB7_3 (b)
(unused) 0 0 0 5 FB7_4 (b)
hcntl0 3 0 0 2 FB7_5 STD 52 I/O O
hcntl1 3 0 0 2 FB7_6 STD 53 I/O O
(unused) 0 0 0 5 FB7_7 (b)
hcs 1 0 0 4 FB7_8 STD 54 I/O O
hd<0> 3 0 0 2 FB7_9 STD 55 I/O I/O
(unused) 0 0 0 5 FB7_10 (b)
hd<1> 3 0 0 2 FB7_11 STD 56 I/O I/O
hd<2> 3 0 0 2 FB7_12 STD 58 I/O I/O
(unused) 0 0 0 5 FB7_13 (b)
hd<3> 3 0 0 2 FB7_14 STD 59 I/O I/O
hd<4> 3 0 0 2 FB7_15 STD 60 I/O I/O
(unused) 0 0 0 5 FB7_16 (b)
hd<5> 3 0 0 2 FB7_17 STD 61 I/O I/O
(unused) 0 0 0 5 FB7_18 (b)
Signals Used by Logic in Function Block
1: byteflage 8: hd<3> 15: write_data_mtridata_qint<1>
2: cnt1/cnt<1> 9: hd<4> 16: write_data_mtridata_qint<2>
3: cnt1/cnt<2> 10: hd<5> 17: write_data_mtridata_qint<3>
4: cnt1/cnt<3> 11: nastrb 18: write_data_mtridata_qint<4>
5: hd<0> 12: ndstrb 19: write_data_mtridata_qint<5>
6: hd<1> 13: nwrite 20: write_data_mtrien_q<0>
7: hd<2> 14: write_data_mtridata_qint<0>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
hhwil .X........XX............................ 3 3
hcntl0 ..X.......XX............................ 3 3
hcntl1 ...X......XX............................ 3 3
hcs X..........X............................ 2 2
hd<0> X...X.......XX.....X.................... 5 5
hd<1> X....X......X.X....X.................... 5 5
hd<2> X.....X.....X..X...X.................... 5 5
hd<3> X......X....X...X..X.................... 5 5
hd<4> X.......X...X....X.X.................... 5 5
hd<5> X........X..X.....XX.................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 22/32
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB8_1 (b)
hd<6> 3 0 0 2 FB8_2 STD 63 I/O I/O
(unused) 0 0 0 5 FB8_3 (b)
(unused) 0 0 0 5 FB8_4 (b)
hd<7> 3 0 0 2 FB8_5 STD 64 I/O I/O
hd<8> 3 0 0 2 FB8_6 STD 65 I/O I/O
(unused) 0 0 0 5 FB8_7 (b)
hd<9> 3 0 0 2 FB8_8 STD 66 I/O I/O
hd<10> 3 0 0 2 FB8_9 STD 67 I/O I/O
(unused) 0 0 0 5 FB8_10 (b)
hd<11> 3 0 0 2 FB8_11 STD 68 I/O I/O
hd<12> 3 0 0 2 FB8_12 STD 70 I/O I/O
(unused) 0 0 0 5 FB8_13 (b)
hd<13> 3 0 0 2 FB8_14 STD 71 I/O I/O
hd<14> 3 0 0 2 FB8_15 STD 72 I/O I/O
(unused) 0 0 0 5 FB8_16 (b)
hd<15> 3 0 0 2 FB8_17 STD 73 I/O I/O
(unused) 0 0 0 5 FB8_18 (b)
Signals Used by Logic in Function Block
1: byteflage 9: write_data_mtridata_q<14>/write_data_mtridata_q<14>_RSTF
16: write_data_mtridata_qint<3>
2: hd<6> 10: write_data_mtridata_q<15>/write_data_mtridata_q<15>_RSTF
17: write_data_mtridata_qint<4>
3: hd<7> 11: write_data_mtridata_q<8>/write_data_mtridata_q<8>_RSTF
18: write_data_mtridata_qint<5>
4: nwrite 12: write_data_mtridata_q<9>/write_data_mtridata_q<9>_RSTF
19: write_data_mtridata_qint<6>
5: write_data_mtridata_q<10>/write_data_mtridata_q<10>_RSTF
13: write_data_mtridata_qint<0>
20: write_data_mtridata_qint<7>
6: write_data_mtridata_q<11>/write_data_mtridata_q<11>_RSTF
14: write_data_mtridata_qint<1>
21: write_data_mtrien_q<0>
7: write_data_mtridata_q<12>/write_data_mtridata_q<12>_RSTF
15: write_data_mtridata_qint<2>
22: write_data_mtrien_q<10>
8: write_data_mtridata_q<13>/write_data_mtridata_q<13>_RSTF
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
hd<6> XX.X..............X.X................... 5 5
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