📄 hpi_epp.rpt
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cpldfit: version F.28 Xilinx Inc.
Fitter Report
Design Name: hpi_epp Date: 7-11-2005, 10:02AM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
77 /144 ( 53%) 202 /720 ( 28%) 51 /144 ( 35%) 33 /81 ( 41%) 117/432 ( 27%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 3 3 | I/O : 33 40
Output : 6 6 | GCK/IO : 0 3
Bidirectional : 24 24 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 33 33
MACROCELL RESOURCES:
Total Macrocells Available 144
Registered Macrocells 51
Non-registered Macrocell driving I/O 10
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 77 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 77 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
byteflage 3 3 FB5_12 STD FAST 42 I/O O RESET
cnt1/cnt<0> 2 2 FB5_8 STD 39 I/O (b) RESET
cnt1/cnt<1> 3 3 FB5_16 STD (b) (b) RESET
cnt1/cnt<2> 4 6 FB5_18 STD (b) (b) RESET
cnt1/cnt<3> 3 5 FB5_15 STD 46 I/O (b) RESET
hcntl0 3 3 FB7_5 STD FAST 52 I/O O RESET
hcntl1 3 3 FB7_6 STD FAST 53 I/O O RESET
hcs 1 2 FB7_8 STD FAST 54 I/O O
hd<0> 3 5 FB7_9 STD FAST 55 I/O I/O
hd<10> 3 5 FB8_9 STD FAST 67 I/O I/O RESET
hd<11> 3 5 FB8_11 STD FAST 68 I/O I/O RESET
hd<12> 3 5 FB8_12 STD FAST 70 I/O I/O RESET
hd<13> 3 5 FB8_14 STD FAST 71 I/O I/O RESET
hd<14> 3 5 FB8_15 STD FAST 72 I/O I/O RESET
hd<15> 3 5 FB8_17 STD FAST 73 I/O I/O RESET
hd<1> 3 5 FB7_11 STD FAST 56 I/O I/O
hd<2> 3 5 FB7_12 STD FAST 58 I/O I/O
hd<3> 3 5 FB7_14 STD FAST 59 I/O I/O
hd<4> 3 5 FB7_15 STD FAST 60 I/O I/O
hd<5> 3 5 FB7_17 STD FAST 61 I/O I/O
hd<6> 3 5 FB8_2 STD FAST 63 I/O I/O
hd<7> 3 5 FB8_5 STD FAST 64 I/O I/O
hd<8> 3 5 FB8_6 STD FAST 65 I/O I/O RESET
hd<9> 3 5 FB8_8 STD FAST 66 I/O I/O RESET
hhwil 3 3 FB7_2 STD FAST 50 I/O O RESET
hpi_rw 1 1 FB5_17 STD FAST 49 I/O O
pd<0> 3 3 FB1_2 STD FAST 11 I/O I/O RESET
pd<1> 3 3 FB1_3 STD FAST 12 I/O I/O RESET
pd<2> 3 3 FB1_5 STD FAST 13 I/O I/O RESET
pd<3> 3 3 FB1_6 STD FAST 14 I/O I/O RESET
pd<4> 3 3 FB1_8 STD FAST 15 I/O I/O RESET
pd<5> 3 3 FB1_9 STD FAST 16 I/O I/O RESET
pd<6> 3 3 FB1_11 STD FAST 17 I/O I/O RESET
pd<7> 3 3 FB1_12 STD FAST 18 I/O I/O RESET
read_data_bufferdata<0> 3 4 FB1_18 STD (b) (b) RESET
read_data_bufferdata<10> 3 4 FB2_18 STD (b) (b) RESET
read_data_bufferdata<11> 3 4 FB5_14 STD 43 I/O (b) RESET
read_data_bufferdata<12> 3 4 FB5_13 STD (b) (b) RESET
read_data_bufferdata<13> 3 4 FB5_11 STD 41 I/O (b) RESET
read_data_bufferdata<14> 3 4 FB5_10 STD (b) (b) RESET
read_data_bufferdata<15> 3 4 FB5_9 STD 40 I/O (b) RESET
read_data_bufferdata<1> 3 4 FB2_17 STD 10 I/O (b) RESET
read_data_bufferdata<2> 3 4 FB2_16 STD (b) (b) RESET
read_data_bufferdata<3> 3 4 FB2_15 STD 9 I/O I RESET
read_data_bufferdata<4> 3 4 FB2_14 STD 8 I/O I RESET
read_data_bufferdata<5> 3 4 FB2_13 STD (b) (b) RESET
read_data_bufferdata<6> 3 4 FB3_18 STD (b) (b) RESET
read_data_bufferdata<7> 3 4 FB3_17 STD 34 I/O (b) RESET
read_data_bufferdata<8> 3 4 FB3_16 STD (b) (b) RESET
read_data_bufferdata<9> 3 4 FB3_15 STD 33 I/O (b) RESET
read_data_mtridata_pd<0>/read_data_mtridata_pd<0>_RSTF 3 5 FB1_17 STD 22 GCK/I/O (b)
read_data_mtridata_pd<1>/read_data_mtridata_pd<1>_SETF 2 5 FB2_12 STD 7 I/O I
read_data_mtridata_pd<2>/read_data_mtridata_pd<2>_SETF 2 5 FB2_11 STD 6 I/O (b)
read_data_mtridata_pd<3>/read_data_mtridata_pd<3>_SETF 2 5 FB2_10 STD (b) (b)
read_data_mtridata_pd<4>/read_data_mtridata_pd<4>_SETF 2 5 FB2_9 STD 4 GTS/I/O (b)
read_data_mtridata_pd<5>/read_data_mtridata_pd<5>_SETF 2 5 FB5_7 STD (b) (b)
read_data_mtridata_pd<6>/read_data_mtridata_pd<6>_SETF 2 5 FB5_6 STD 37 I/O (b)
read_data_mtridata_pd<7>/read_data_mtridata_pd<7>_RSTF 3 5 FB1_16 STD (b) (b)
read_data_mtrien_pd 2 2 FB1_15 STD 20 I/O (b) RESET
write_data_mtridata_q<10>/write_data_mtridata_q<10>_RSTF 2 3 FB3_14 STD 32 I/O (b)
write_data_mtridata_q<11>/write_data_mtridata_q<11>_RSTF 2 3 FB3_13 STD (b) (b)
write_data_mtridata_q<12>/write_data_mtridata_q<12>_RSTF 2 3 FB3_12 STD 30 I/O (b)
write_data_mtridata_q<13>/write_data_mtridata_q<13>_RSTF 2 3 FB3_11 STD 29 I/O (b)
write_data_mtridata_q<14>/write_data_mtridata_q<14>_RSTF 2 3 FB3_10 STD (b) (b)
write_data_mtridata_q<15>/write_data_mtridata_q<15>_RSTF 2 3 FB3_9 STD 28 I/O (b)
write_data_mtridata_q<8>/write_data_mtridata_q<8>_RSTF 2 3 FB3_8 STD 27 GCK/I/O (b)
write_data_mtridata_q<9>/write_data_mtridata_q<9>_RSTF 2 3 FB3_7 STD (b) (b)
write_data_mtridata_qint<0> 2 2 FB3_6 STD 25 I/O (b) RESET
write_data_mtridata_qint<1> 2 2 FB3_5 STD 24 I/O (b) RESET
write_data_mtridata_qint<2> 2 2 FB4_18 STD (b) (b) RESET
write_data_mtridata_qint<3> 2 2 FB4_17 STD 97 I/O (b) RESET
write_data_mtridata_qint<4> 2 2 FB4_16 STD (b) (b) RESET
write_data_mtridata_qint<5> 2 2 FB4_15 STD 96 I/O (b) RESET
write_data_mtridata_qint<6> 2 2 FB4_14 STD 95 I/O (b) RESET
write_data_mtridata_qint<7> 2 2 FB4_13 STD (b) (b) RESET
write_data_mtrien_q<0> 2 2 FB1_14 STD 19 I/O (b) RESET
write_data_mtrien_q<10> 2 2 FB1_13 STD (b) (b) RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
nastrb FB2_14 8 I/O I
ndstrb FB2_12 7 I/O I
nwrite FB2_15 9 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 14 17 17 39 0/8 11
FB2 10 17 17 26 0/0 10
FB3 14 17 17 32 0/0 10
FB4 6 7 7 12 0/0 10
FB5 13 17 17 35 2/0 10
FB6 0 0 0 0 0/0 10
FB7 10 20 20 28 4/6 10
FB8 10 22 22 30 0/10 10
---- ----- ----- -----
77 202 6/24 81
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 17/37
Number of signals used by logic mapping into function block: 17
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
pd<0> 3 0 0 2 FB1_2 STD 11 I/O I/O
pd<1> 3 0 0 2 FB1_3 STD 12 I/O I/O
(unused) 0 0 0 5 FB1_4 (b)
pd<2> 3 0 0 2 FB1_5 STD 13 I/O I/O
pd<3> 3 0 0 2 FB1_6 STD 14 I/O I/O
(unused) 0 0 0 5 FB1_7 (b)
pd<4> 3 0 0 2 FB1_8 STD 15 I/O I/O
pd<5> 3 0 0 2 FB1_9 STD 16 I/O I/O
(unused) 0 0 0 5 FB1_10 (b)
pd<6> 3 0 0 2 FB1_11 STD 17 I/O I/O
pd<7> 3 0 0 2 FB1_12 STD 18 I/O I/O
write_data_mtrien_q<10>
2 0 0 3 FB1_13 STD (b) (b)
write_data_mtrien_q<0>
2 0 0 3 FB1_14 STD 19 I/O (b)
read_data_mtrien_pd 2 0 0 3 FB1_15 STD 20 I/O (b)
read_data_mtridata_pd<7>/read_data_mtridata_pd<7>_RSTF
3 0 0 2 FB1_16 STD (b) (b)
read_data_mtridata_pd<0>/read_data_mtridata_pd<0>_RSTF
3 0 0 2 FB1_17 STD 22 GCK/I/O (b)
read_data_bufferdata<0>
3 0 0 2 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: byteflage 7: read_data_bufferdata<7>
13: read_data_mtridata_pd<4>/read_data_mtridata_pd<4>_SETF
2: hd<0>.PIN 8: read_data_bufferdata<8>
14: read_data_mtridata_pd<5>/read_data_mtridata_pd<5>_SETF
3: ndstrb 9: read_data_mtridata_pd<0>/read_data_mtridata_pd<0>_RSTF
15: read_data_mtridata_pd<6>/read_data_mtridata_pd<6>_SETF
4: nwrite 10: read_data_mtridata_pd<1>/read_data_mtridata_pd<1>_SETF
16: read_data_mtridata_pd<7>/read_data_mtridata_pd<7>_RSTF
5: read_data_bufferdata<0>
11: read_data_mtridata_pd<2>/read_data_mtridata_pd<2>_SETF
17: read_data_mtrien_pd
6: read_data_bufferdata<15>
12: read_data_mtridata_pd<3>/read_data_mtridata_pd<3>_SETF
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
pd<0> ...X....X.......X....................... 3 3
pd<1> ...X.....X......X....................... 3 3
pd<2> ...X......X.....X....................... 3 3
pd<3> ...X.......X....X....................... 3 3
pd<4> ...X........X...X....................... 3 3
pd<5> ...X.........X..X....................... 3 3
pd<6> ...X..........X.X....................... 3 3
pd<7> ...X...........XX....................... 3 3
write_data_mtrien_q<10>
X..X.................................... 2 2
write_data_mtrien_q<0>
X..X.................................... 2 2
read_data_mtrien_pd ..XX.................................... 2 2
read_data_mtridata_pd<7>/read_data_mtridata_pd<7>_RSTF
X.XX.XX................................. 5 5
read_data_mtridata_pd<0>/read_data_mtridata_pd<0>_RSTF
X.XXX..X................................ 5 5
read_data_bufferdata<0>
XXXX.................................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
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