hpi_epp.mod

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MODEL
MODEL_VERSION "v1998.8";
DESIGN "hpi_epp";

/* port names and type */
INPUT S:PIN9 = nwrite;
INPUT S:PIN8 = nastrb;
INPUT S:PIN7 = ndstrb;
TRIOUT S:PIN55 = hd<0>;
TRIOUT S:PIN67 = hd<10>;
TRIOUT S:PIN68 = hd<11>;
TRIOUT S:PIN70 = hd<12>;
TRIOUT S:PIN71 = hd<13>;
TRIOUT S:PIN72 = hd<14>;
TRIOUT S:PIN73 = hd<15>;
TRIOUT S:PIN56 = hd<1>;
TRIOUT S:PIN58 = hd<2>;
TRIOUT S:PIN59 = hd<3>;
TRIOUT S:PIN60 = hd<4>;
TRIOUT S:PIN61 = hd<5>;
TRIOUT S:PIN63 = hd<6>;
TRIOUT S:PIN64 = hd<7>;
TRIOUT S:PIN65 = hd<8>;
TRIOUT S:PIN66 = hd<9>;
TRIOUT S:PIN11 = pd<0>;
TRIOUT S:PIN12 = pd<1>;
TRIOUT S:PIN13 = pd<2>;
TRIOUT S:PIN14 = pd<3>;
TRIOUT S:PIN15 = pd<4>;
TRIOUT S:PIN16 = pd<5>;
TRIOUT S:PIN17 = pd<6>;
TRIOUT S:PIN18 = pd<7>;
OUTPUT S:PIN42 = byteflage;
OUTPUT S:PIN50 = hhwil;
OUTPUT S:PIN52 = hcntl0;
OUTPUT S:PIN53 = hcntl1;
OUTPUT S:PIN54 = hcs;
OUTPUT S:PIN49 = hpi_rw;

/* timing arc definitions */
ndstrb_hcs_delay: DELAY ndstrb hcs;
nwrite_hd<0>_delay: DELAY (ENABLE_HIGH) nwrite hd<0>;
nwrite_hd<1>_delay: DELAY (ENABLE_HIGH) nwrite hd<1>;
nwrite_hd<2>_delay: DELAY (ENABLE_HIGH) nwrite hd<2>;
nwrite_hd<3>_delay: DELAY (ENABLE_HIGH) nwrite hd<3>;
nwrite_hd<4>_delay: DELAY (ENABLE_HIGH) nwrite hd<4>;
nwrite_hd<5>_delay: DELAY (ENABLE_HIGH) nwrite hd<5>;
nwrite_hd<6>_delay: DELAY (ENABLE_HIGH) nwrite hd<6>;
nwrite_hd<7>_delay: DELAY (ENABLE_HIGH) nwrite hd<7>;
nwrite_hpi_rw_delay: DELAY nwrite hpi_rw;
ndstrb_hd<0>_delay: DELAY (ENABLE_HIGH) ndstrb hd<0>;
ndstrb_hd<1>_delay: DELAY (ENABLE_HIGH) ndstrb hd<1>;
ndstrb_hd<2>_delay: DELAY (ENABLE_HIGH) ndstrb hd<2>;
ndstrb_hd<3>_delay: DELAY (ENABLE_HIGH) ndstrb hd<3>;
ndstrb_hd<4>_delay: DELAY (ENABLE_HIGH) ndstrb hd<4>;
ndstrb_hd<5>_delay: DELAY (ENABLE_HIGH) ndstrb hd<5>;
ndstrb_hd<6>_delay: DELAY (ENABLE_HIGH) ndstrb hd<6>;
ndstrb_hd<7>_delay: DELAY (ENABLE_HIGH) ndstrb hd<7>;
ndstrb_byteflage_delay: DELAY ndstrb byteflage;
ndstrb_hhwil_delay: DELAY ndstrb hhwil;
ndstrb_hcntl0_delay: DELAY ndstrb hcntl0;
ndstrb_hcntl1_delay: DELAY ndstrb hcntl1;
ndstrb_hcs_delay: DELAY ndstrb hcs;

/* timing check arc definitions */
hd<0>_ndstrb_setup: SETUP(POSEDGE) hd<0> ndstrb;
hd<10>_ndstrb_setup: SETUP(POSEDGE) hd<10> ndstrb;
hd<11>_ndstrb_setup: SETUP(POSEDGE) hd<11> ndstrb;
hd<12>_ndstrb_setup: SETUP(POSEDGE) hd<12> ndstrb;
hd<13>_ndstrb_setup: SETUP(POSEDGE) hd<13> ndstrb;
hd<14>_ndstrb_setup: SETUP(POSEDGE) hd<14> ndstrb;
hd<15>_ndstrb_setup: SETUP(POSEDGE) hd<15> ndstrb;
hd<1>_ndstrb_setup: SETUP(POSEDGE) hd<1> ndstrb;
hd<2>_ndstrb_setup: SETUP(POSEDGE) hd<2> ndstrb;
hd<3>_ndstrb_setup: SETUP(POSEDGE) hd<3> ndstrb;
hd<4>_ndstrb_setup: SETUP(POSEDGE) hd<4> ndstrb;
hd<5>_ndstrb_setup: SETUP(POSEDGE) hd<5> ndstrb;
hd<6>_ndstrb_setup: SETUP(POSEDGE) hd<6> ndstrb;
hd<7>_ndstrb_setup: SETUP(POSEDGE) hd<7> ndstrb;
hd<8>_ndstrb_setup: SETUP(POSEDGE) hd<8> ndstrb;
hd<9>_ndstrb_setup: SETUP(POSEDGE) hd<9> ndstrb;
nastrb_ndstrb_setup: SETUP(POSEDGE) nastrb ndstrb;
nwrite_ndstrb_setup: SETUP(POSEDGE) nwrite ndstrb;
pd<0>_ndstrb_setup: SETUP(POSEDGE) pd<0> ndstrb;
pd<1>_ndstrb_setup: SETUP(POSEDGE) pd<1> ndstrb;
pd<2>_ndstrb_setup: SETUP(POSEDGE) pd<2> ndstrb;
pd<3>_ndstrb_setup: SETUP(POSEDGE) pd<3> ndstrb;
pd<4>_ndstrb_setup: SETUP(POSEDGE) pd<4> ndstrb;
pd<5>_ndstrb_setup: SETUP(POSEDGE) pd<5> ndstrb;
pd<6>_ndstrb_setup: SETUP(POSEDGE) pd<6> ndstrb;
pd<7>_ndstrb_setup: SETUP(POSEDGE) pd<7> ndstrb;
hd<0>_ndstrb_hold: HOLD(POSEDGE) hd<0> ndstrb;
hd<10>_ndstrb_hold: HOLD(POSEDGE) hd<10> ndstrb;
hd<11>_ndstrb_hold: HOLD(POSEDGE) hd<11> ndstrb;
hd<12>_ndstrb_hold: HOLD(POSEDGE) hd<12> ndstrb;
hd<13>_ndstrb_hold: HOLD(POSEDGE) hd<13> ndstrb;
hd<14>_ndstrb_hold: HOLD(POSEDGE) hd<14> ndstrb;
hd<15>_ndstrb_hold: HOLD(POSEDGE) hd<15> ndstrb;
hd<1>_ndstrb_hold: HOLD(POSEDGE) hd<1> ndstrb;
hd<2>_ndstrb_hold: HOLD(POSEDGE) hd<2> ndstrb;
hd<3>_ndstrb_hold: HOLD(POSEDGE) hd<3> ndstrb;
hd<4>_ndstrb_hold: HOLD(POSEDGE) hd<4> ndstrb;
hd<5>_ndstrb_hold: HOLD(POSEDGE) hd<5> ndstrb;
hd<6>_ndstrb_hold: HOLD(POSEDGE) hd<6> ndstrb;
hd<7>_ndstrb_hold: HOLD(POSEDGE) hd<7> ndstrb;
hd<8>_ndstrb_hold: HOLD(POSEDGE) hd<8> ndstrb;
hd<9>_ndstrb_hold: HOLD(POSEDGE) hd<9> ndstrb;
nastrb_ndstrb_hold: HOLD(POSEDGE) nastrb ndstrb;
nwrite_ndstrb_hold: HOLD(POSEDGE) nwrite ndstrb;
pd<0>_ndstrb_hold: HOLD(POSEDGE) pd<0> ndstrb;
pd<1>_ndstrb_hold: HOLD(POSEDGE) pd<1> ndstrb;
pd<2>_ndstrb_hold: HOLD(POSEDGE) pd<2> ndstrb;
pd<3>_ndstrb_hold: HOLD(POSEDGE) pd<3> ndstrb;
pd<4>_ndstrb_hold: HOLD(POSEDGE) pd<4> ndstrb;
pd<5>_ndstrb_hold: HOLD(POSEDGE) pd<5> ndstrb;
pd<6>_ndstrb_hold: HOLD(POSEDGE) pd<6> ndstrb;
pd<7>_ndstrb_hold: HOLD(POSEDGE) pd<7> ndstrb;

ENDMODEL