hpi_epp.syr

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Release 5.2i - xst F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: hpi_epp.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : hpi_epp.prj
Input Format                       : VHDL
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : hpi_epp
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Entity Name                        : hpi_epp
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : lower

---- Other Options
cross_clock_analysis               : NO
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/工作文档/myepp5_23/hpi_epp.vhd in Library work.
Entity <count16> (Architecture <count16_arch>) compiled.
Entity <latch> (Architecture <latch_arch>) compiled.
Entity <read> (Architecture <read_arch>) compiled.
Entity <hpi_epp> (Architecture <hpi_epp_arch>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <hpi_epp> (Architecture <hpi_epp_arch>).
INFO:Xst:1304 - Contents of register <hd> in unit <hpi_epp> never changes during circuit operation. The register is replaced by logic.
Entity <hpi_epp> analyzed. Unit <hpi_epp> generated.

Analyzing Entity <count16> (Architecture <count16_arch>).
Entity <count16> analyzed. Unit <count16> generated.

Analyzing Entity <latch> (Architecture <latch_arch>).
WARNING:Xst:819 - D:/工作文档/myepp5_23/hpi_epp.vhd line 76: The following signals are missing in the process sensitivity list:
   q0, qint<7>, qint<6>, qint<5>, qint<4>, qint<3>, qint<2>, qint<1>, qint<0>.
Entity <latch> analyzed. Unit <latch> generated.

Analyzing Entity <read> (Architecture <read_arch>).
WARNING:Xst:819 - D:/工作文档/myepp5_23/hpi_epp.vhd line 112: The following signals are missing in the process sensitivity list:
   bufferdata<7>, bufferdata<6>, bufferdata<5>, bufferdata<4>, bufferdata<3>, bufferdata<2>, bufferdata<1>, bufferdata<0>, bufferdata<15>, bufferdata<14>, bufferdata<13>, bufferdata<12>, bufferdata<11>, bufferdata<10>, bufferdata<9>, bufferdata<8>.
Entity <read> analyzed. Unit <read> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <read>.
    Related source file is D:/工作文档/myepp5_23/hpi_epp.vhd.
WARNING:Xst:736 - Found 8-bit latch for signal <Mtridata_pd> created at line 119.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_pd> created at line 119.
    Found 8-bit tristate buffer for signal <pd>.
    Found 16-bit register for signal <bufferdata>.
    Summary:
	inferred   8 Tristate(s).
Unit <read> synthesized.


Synthesizing Unit <latch>.
    Related source file is D:/工作文档/myepp5_23/hpi_epp.vhd.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<7>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<6>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<5>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<4>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<3>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<2>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<1>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<0>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<15>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<14>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<13>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<12>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<11>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<10>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<9>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_q<8>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<7>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<6>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<5>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<4>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<3>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<2>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<1>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<0>> created at line 86.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<15>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<14>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<13>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<12>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<11>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<10>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<9>> created at line 88.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_q<8>> created at line 88.
    Found 16-bit tristate buffer for signal <q>.
    Found 8-bit register for signal <Mtridata_qint> created at line 80.
    Found 8-bit tristate buffer for signal <qint>.
    Summary:
	inferred  24 Tristate(s).
Unit <latch> synthesized.


Synthesizing Unit <count16>.
    Related source file is D:/工作文档/myepp5_23/hpi_epp.vhd.
    Found 1-bit register for signal <q0>.
    Found 1-bit register for signal <q1>.
    Found 1-bit register for signal <q2>.
    Found 1-bit register for signal <q3>.
    Found 4-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   4 D-type flip-flop(s).
Unit <count16> synthesized.


Synthesizing Unit <hpi_epp>.
    Related source file is D:/工作文档/myepp5_23/hpi_epp.vhd.
    Found 16-bit tristate buffer for signal <hd>.
    Summary:
	inferred  16 Tristate(s).
Unit <hpi_epp> synthesized.