hpi_epp.tim

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                           Performance Summary Report
                           --------------------------

Design:     hpi_epp
Device:     XC95144XL-10-TQ100
Speed File: Version 3.0
Program:    Timing Report Generator:  version F.28
Date:       Mon Jul 11 10:02:34 2005

Performance Summary:

Pad to Pad (tPD)                          :         10.0ns (1 macrocell levels)
Pad 'nwrite' to Pad 'hd<0>'                                       

Clock net 'byteflage.Q' path delays:

Setup to Clock at the Pad (tSU)           :          0.4ns (0 macrocell levels)
Data signal 'hd<0>' to DFF D input Pin at 'read_data_bufferdata<0>.D'
Clock pad 'byteflage.Q'                                           (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'ndstrb' path delays:

Clock Pad to Output Pad (tCO)             :         17.9ns (2 macrocell levels)
Clock Pad 'ndstrb' to Output Pad 'hd<0>'                          (Pterm Clock)

Clock to Setup (tCYC)                     :         10.0ns (1 macrocell levels)
Clock to Q, net 'cnt1/cnt<0>.Q' to DFF Setup(D) at 'byteflage.D'  (Pterm Clock)
Target FF drives output net 'q0$Q'

Setup to Clock at the Pad (tSU)           :          2.1ns (0 macrocell levels)
Data signal 'nastrb' to DFF D input Pin at 'byteflage.CE'
Clock pad 'ndstrb'                                                (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From      n     n
 \          d     w
  \         s     r
   \        t     i
    \       r     t
     \      b     e
      \            
  To   \------------

hcs      10.0      
hd<0>          10.0
hd<1>          10.0
hd<2>          10.0
hd<3>          10.0
hd<4>          10.0
hd<5>          10.0
hd<6>          10.0
hd<7>          10.0
hpi_rw         10.0

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From        n
 \            d
  \           s
   \          t
    \         r
     \        b
      \        
       \       
        \      
  To     \------

byteflage  10.2
hcntl0     10.2
hcntl1     10.2
hcs        17.9
hd<0>      17.9
hd<1>      17.9
hd<2>      17.9
hd<3>      17.9
hd<4>      17.9
hd<5>      17.9
hd<6>      17.9
hd<7>      17.9
hhwil      10.2

--------------------------------------------------------------------------------
                   Setup to Clock at Pad (tSU or tSUF) (nsec)

\ From      n
 \          d
  \         s
   \        t
    \       r
     \      b
      \      
  To   \------

hd<0>     2.1
hd<10>    2.1
hd<11>    2.1
hd<12>    2.1
hd<13>    2.1
hd<14>    2.1
hd<15>    2.1
hd<1>     2.1
hd<2>     2.1
hd<3>     2.1
hd<4>     2.1
hd<5>     2.1
hd<6>     2.1
hd<7>     2.1
hd<8>     2.1
hd<9>     2.1
nastrb    2.1
nwrite    2.1
pd<0>     2.1
pd<1>     2.1
pd<2>     2.1
pd<3>     2.1
pd<4>     2.1
pd<5>     2.1
pd<6>     2.1
pd<7>     2.1

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                (Clock: ndstrb)

\ From            c     c     c     c
 \                n     n     n     n
  \               t     t     t     t
   \              1     1     1     1
    \             /     /     /     /
     \            c     c     c     c
      \           n     n     n     n
       \          t     t     t     t
        \         <     <     <     <
         \        0     1     2     3
          \       >     >     >     >
           \      .     .     .     .
            \     Q     Q     Q     Q
  To         \------------------------

byteflage.D    10.0                  
cnt1/cnt<1>.D  10.0                  
cnt1/cnt<2>.D  10.0  10.0  10.0  10.0
cnt1/cnt<3>.D  10.0  10.0  10.0      
hcntl0.D                   10.0      
hcntl1.D                         10.0
hhwil.D              10.0            

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU or tSUF) -     Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and ends at register 
                                          (Fast Input Register for tSUF) D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. Pin-to-pin setup 
                                          requirement is not reported or 
                                          guaranteed for product-term clocks 
                                          derived from macrocell feedback 
                                          signals. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.