shuzizhong.npl

EDA课程设计（带完整设计报告）

JDF G
// Created by Project Navigator ver 1.0
PROJECT shuzizhong
DESIGN shuzizhong
DEVFAM spartan2
DEVFAMTIME 1228630260
DEVICE xc2s200
DEVICETIME 1228630260
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE second.vhdl
STIMULUS a.tbw
SOURCE minute.vhdl
SOURCE alm.vhdl
STIMULUS dd.tbw
SOURCE yima.vhdl
STIMULUS e.tbw
SOURCE main.vhdl
SOURCE hour1.vhdl
STIMULUS maintwb.tbw
SOURCE jhgjgh.vhdl
DEPASSOC topclock topclock.ucf
[STATUS-ALL]
topclock.bitgenGroup=OK,0
[STRATEGY-LIST]
Normal=True