jhgjgh.syr

EDA课程设计（带完整设计报告）

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: jhgjgh.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : jhgjgh.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : jhgjgh
Output Format                      : NGC
Target Device                      : xc2s200-6-pq208

---- Source Options
Top Module Name                    : jhgjgh
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : jhgjgh.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/chenyi/shuzizhong/jhgjgh.vhdl in Library work.
Entity <jhgjgh> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <jhgjgh> (Architecture <behavioral>).
Entity <jhgjgh> analyzed. Unit <jhgjgh> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <jhgjgh>.
    Related source file is D:/chenyi/shuzizhong/jhgjgh.vhdl.
    Found 1-bit register for signal <clks>.
    Found 32-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jhgjgh> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 1
 1-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <jhgjgh> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block jhgjgh, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : jhgjgh.ngr
Top Level Output File Name         : jhgjgh
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 3

Macro Statistics :
# Registers                        : 1
#      1-bit register              : 1
# Counters                         : 1
#      32-bit up counter           : 1

Cell Usage :
# BELS                             : 113
#      GND                         : 1
#      LUT1                        : 2
#      LUT2                        : 1
#      LUT3                        : 2
#      LUT3_L                      : 6
#      LUT4                        : 6
#      LUT4_D                      : 6
#      LUT4_L                      : 24
#      MUXCY                       : 32
#      VCC                         : 1
#      XORCY                       : 32
# FlipFlops/Latches                : 33
#      FDCE                        : 1
#      FDE                         : 32
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 2
#      IBUF                        : 1
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-6 

 Number of Slices:                      26  out of   2352     1%  
 Number of Slice Flip Flops:            33  out of   4704     0%  
 Number of 4 input LUTs:                47  out of   4704     0%  
 Number of bonded IOBs:                  2  out of    144     1%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 33    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 11.654ns (Maximum Frequency: 85.807MHz)
   Minimum input arrival time before clock: 5.127ns
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               11.654ns (Levels of Logic = 10)
  Source:            cnt_0 (FF)
  Destination:       cnt_31 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_0 to cnt_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.085   1.206  cnt_0 (cnt_0)
     LUT4:I0->O            2   0.549   1.206  _n0001123 (CHOICE157)
     LUT4:I2->O           13   0.549   2.250  _n0001149 (CHOICE166)
     LUT4_D:I3->O          7   0.549   1.755  _n0001165 (_n0001)
     LUT3_L:I0->LO         1   0.549   0.000  cnt_inst_lut3_261 (cnt_inst_lut3_26)
     MUXCY:S->O            1   0.659   0.000  cnt_inst_cy_27 (cnt_inst_cy_27)
     MUXCY:CI->O           1   0.042   0.000  cnt_inst_cy_28 (cnt_inst_cy_28)
     MUXCY:CI->O           1   0.042   0.000  cnt_inst_cy_29 (cnt_inst_cy_29)
     MUXCY:CI->O           1   0.042   0.000  cnt_inst_cy_30 (cnt_inst_cy_30)
     MUXCY:CI->O           0   0.042   0.000  cnt_inst_cy_31 (cnt_inst_cy_31)
     XORCY:CI->O           1   0.420   0.000  cnt_inst_sum_31 (cnt_inst_sum_31)
     FDE:D                     0.709          cnt_31
    ----------------------------------------
    Total                     11.654ns (5.237ns logic, 6.417ns route)
                                       (44.9% logic, 55.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              5.127ns (Levels of Logic = 1)
  Source:            reset (PAD)
  Destination:       cnt_30 (FF)
  Destination Clock: clk rising

  Data Path: reset to cnt_30
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            33   0.776   3.465  reset_IBUF (reset_IBUF)
     FDE:CE                    0.886          cnt_0
    ----------------------------------------
    Total                      5.127ns (1.662ns logic, 3.465ns route)
                                       (32.4% logic, 67.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.959ns (Levels of Logic = 1)
  Source:            clks (FF)
  Destination:       q (PAD)
  Source Clock:      clk rising

  Data Path: clks to q
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   1.085   1.206  clks (clks)
     OBUF:I->O                 4.668          q_OBUF (q)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
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