minute1_timesim.vhd

EDA课程设计（带完整设计报告）

      ADR2 => VCC,
      ADR3 => CHOICE22,
      O => Min2_0_FROM
    );
  Min2_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"CF00"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => N438,
      ADR2 => CHOICE22,
      ADR3 => Min2_0,
      O => Min2_inst_lut3_01_O
    );
  Min2_0_COUTUSED : X_BUF
    port map (
      I => Min2_0_CYMUXG,
      O => Min2_inst_cy_5
    );
  Min2_0_XUSED : X_BUF
    port map (
      I => Min2_0_FROM,
      O => Q_n0004_SW113_O
    );
  Min2_inst_cy_5_21 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => Min2_inst_cy_4,
      SEL => Min2_inst_lut3_01_O,
      O => Min2_0_CYMUXG
    );
  Min2_inst_sum_4_22 : X_XOR2
    port map (
      I0 => Min2_inst_cy_4,
      I1 => Min2_inst_lut3_01_O,
      O => Min2_inst_sum_4
    );
  Min2_0_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => Min2_0_SRMUX_OUTPUTNOT
    );
  Min2_1_LOGIC_ZERO_23 : X_ZERO
    port map (
      O => Min2_1_LOGIC_ZERO
    );
  Min2_inst_cy_6_24 : X_MUX2
    port map (
      IA => Min2_1_LOGIC_ZERO,
      IB => Min2_1_CYINIT,
      SEL => Min2_1_FROM,
      O => Min2_inst_cy_6
    );
  Min2_inst_sum_5_25 : X_XOR2
    port map (
      I0 => Min2_1_CYINIT,
      I1 => Min2_1_FROM,
      O => Min2_inst_sum_5
    );
  Min2_1_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Min2_1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Min2_1_FROM
    );
  Min2_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"CC44"
    )
    port map (
      ADR0 => CHOICE22,
      ADR1 => Min2_2,
      ADR2 => VCC,
      ADR3 => N438,
      O => Min2_inst_lut3_21_O
    );
  Min2_1_COUTUSED : X_BUF
    port map (
      I => Min2_1_CYMUXG,
      O => Min2_inst_cy_7
    );
  Min2_inst_cy_7_26 : X_MUX2
    port map (
      IA => Min2_1_LOGIC_ZERO,
      IB => Min2_inst_cy_6,
      SEL => Min2_inst_lut3_21_O,
      O => Min2_1_CYMUXG
    );
  Min2_inst_sum_6_27 : X_XOR2
    port map (
      I0 => Min2_inst_cy_6,
      I1 => Min2_inst_lut3_21_O,
      O => Min2_inst_sum_6
    );
  Min2_1_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => Min2_1_SRMUX_OUTPUTNOT
    );
  Min2_1_CYINIT_28 : X_BUF
    port map (
      I => Min2_inst_cy_5,
      O => Min2_1_CYINIT
    );
  Min2_inst_sum_7_29 : X_XOR2
    port map (
      I0 => Min2_3_CYINIT,
      I1 => Min2_3_rt,
      O => Min2_inst_sum_7
    );
  Min2_3_rt_30 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Min2_3,
      O => Min2_3_rt
    );
  Min2_3_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => Min2_3_SRMUX_OUTPUTNOT
    );
  Min2_3_CYINIT_31 : X_BUF
    port map (
      I => Min2_inst_cy_7,
      O => Min2_3_CYINIT
    );
  Ker4361 : X_LUT4
    generic map(
      INIT => X"FFBF"
    )
    port map (
      ADR0 => Min1_2,
      ADR1 => Min1_3,
      ADR2 => Min1_0,
      ADR3 => Min1_1,
      O => Min1_2_FROM
    );
  Q_n0003_2_1 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => Q_n0010(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => N438,
      O => Q_n0003_2_1_O
    );
  Min1_2_XUSED : X_BUF
    port map (
      I => Min1_2_FROM,
      O => N438
    );
  Min1_2_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => Min1_2_SRMUX_OUTPUTNOT
    );
  Q_n0003_3_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Q_n0010(3),
      ADR3 => N438,
      O => Q_n0003_3_1_O
    );
  Min1_3_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => Min1_3_SRMUX_OUTPUTNOT
    );
  Q_n0003_1_1 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => N438,
      ADR1 => Q_n0010(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_n0003_1_1_O
    );
  Min1_0_BXMUX : X_INV
    port map (
      I => Min1_0,
      O => Min1_0_BXMUXNOT
    );
  Min1_0_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => Min1_0_SRMUX_OUTPUTNOT
    );
  Q_n0004_SW110 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Min2_1,
      ADR1 => Min2_3,
      ADR2 => Min2_0,
      ADR3 => Min2_2,
      O => CHOICE22_GROM
    );
  CHOICE22_YUSED : X_BUF
    port map (
      I => CHOICE22_GROM,
      O => CHOICE22
    );
  Q_n00071 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => Min1_2,
      ADR1 => Min1_1,
      ADR2 => Min1_0,
      ADR3 => Min1_3,
      O => Q_n0007_GROM
    );
  Q_n0007_YUSED : X_BUF
    port map (
      I => Q_n0007_GROM,
      O => Q_n0007
    );
  Enmin_32 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Enmin_OD,
      CE => VCC,
      CLK => clkm_BUFGP,
      SET => GND,
      RST => Enmin_OFF_RST,
      O => Enmin_OBUF
    );
  Enmin_OFF_RSTOR : X_OR2
    port map (
      I0 => Enmin_SRMUXNOT,
      I1 => GSR,
      O => Enmin_OFF_RST
    );
  Min2_0_33 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Min2_inst_sum_4,
      CE => Q_n0007,
      CLK => clkm_BUFGP,
      SET => GND,
      RST => Min2_0_FFY_RST,
      O => Min2_0
    );
  Min2_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Min2_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Min2_0_FFY_RST
    );
  Min2_2_34 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Min2_inst_sum_6,
      CE => Q_n0007,
      CLK => clkm_BUFGP,
      SET => GND,
      RST => Min2_1_FFY_RST,
      O => Min2_2
    );
  Min2_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Min2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Min2_1_FFY_RST
    );
  Min2_1_35 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Min2_inst_sum_5,
      CE => Q_n0007,
      CLK => clkm_BUFGP,
      SET => GND,
      RST => Min2_1_FFX_RST,
      O => Min2_1
    );
  Min2_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Min2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Min2_1_FFX_RST
    );
  Min2_3_36 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Min2_inst_sum_7,
      CE => Q_n0007,
      CLK => clkm_BUFGP,
      SET => GND,
      RST => Min2_3_FFX_RST,
      O => Min2_3
    );
  Min2_3_FFX_RSTOR : X_OR2
    port map (
      I0 => Min2_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Min2_3_FFX_RST
    );
  Min1_2_37 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003_2_1_O,
      CE => VCC,
      CLK => clkm_BUFGP,
      SET => GND,
      RST => Min1_2_FFY_RST,
      O => Min1_2
    );
  Min1_2_FFY_RSTOR : X_OR2
    port map (
      I0 => Min1_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Min1_2_FFY_RST
    );
  Min1_3_38 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003_3_1_O,
      CE => VCC,
      CLK => clkm_BUFGP,
      SET => GND,
      RST => Min1_3_FFY_RST,
      O => Min1_3
    );
  Min1_3_FFY_RSTOR : X_OR2
    port map (
      I0 => Min1_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Min1_3_FFY_RST
    );
  Min1_1_39 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003_1_1_O,
      CE => VCC,
      CLK => clkm_BUFGP,
      SET => GND,
      RST => Min1_0_FFY_RST,
      O => Min1_1
    );
  Min1_0_FFY_RSTOR : X_OR2
    port map (
      I0 => Min1_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Min1_0_FFY_RST
    );
  Min1_0_40 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Min1_0_BXMUXNOT,
      CE => VCC,
      CLK => clkm_BUFGP,
      SET => GND,
      RST => Min1_0_FFX_RST,
      O => Min1_0
    );
  Min1_0_FFX_RSTOR : X_OR2
    port map (
      I0 => Min1_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Min1_0_FFX_RST
    );
  clkm_BUF : X_CKBUF
    port map (
      I => clkm,
      O => clkm_BUFGP_IBUFG
    );
  clkm_BUFGP_BUFG_BUF : X_CKBUF
    port map (
      I => clkm_BUFGP_IBUFG,
      O => clkm_BUFGP
    );
  PWR_GND_0_F : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_0_FROM
    );
  PWR_GND_0_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_0_GROM
    );
  PWR_GND_0_XUSED : X_BUF
    port map (
      I => PWR_GND_0_FROM,
      O => GLOBAL_LOGIC1_0
    );
  PWR_GND_0_YUSED : X_BUF
    port map (
      I => PWR_GND_0_GROM,
      O => GLOBAL_LOGIC0
    );
  PWR_GND_1_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_GND_1_GROM
    );
  PWR_GND_1_YUSED : X_BUF
    port map (
      I => PWR_GND_1_GROM,
      O => GLOBAL_LOGIC0_0
    );
  PWR_VCC_0_F : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PWR_VCC_0_FROM
    );
  PWR_VCC_0_XUSED : X_BUF
    port map (
      I => PWR_VCC_0_FROM,
      O => GLOBAL_LOGIC1
    );
  NlwBlock_minute1_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_minute1_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;