minute1_timesim.vhd

EDA课程设计（带完整设计报告）

-- Xilinx Vhdl netlist produced by netgen application (version G.28)
-- Command       : -intstyle ise -s 6 -pcf minute1.pcf -ngm minute1.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim minute1.ncd minute1_timesim.vhd 
-- Input file    : minute1.ncd
-- Output file   : minute1_timesim.vhd
-- Design name   : minute1
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : 2s50epq208-6 (PRODUCTION 1.17 2003-12-13)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity minute1 is
  port (
    Enmin : out STD_LOGIC; 
    clkm : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    Min2 : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    Min1 : out STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end minute1;

architecture Structure of minute1 is
  signal Min1_0 : STD_LOGIC; 
  signal clkm_BUFGP_IBUFG : STD_LOGIC; 
  signal Min1_1 : STD_LOGIC; 
  signal Min1_2 : STD_LOGIC; 
  signal Min1_3 : STD_LOGIC; 
  signal Min2_0 : STD_LOGIC; 
  signal Min2_1 : STD_LOGIC; 
  signal Min2_2 : STD_LOGIC; 
  signal Min2_3 : STD_LOGIC; 
  signal reset_IBUF : STD_LOGIC; 
  signal clkm_BUFGP : STD_LOGIC; 
  signal Q_n0004_SW113_O : STD_LOGIC; 
  signal Madd_n0010_inst_cy_1 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal Q_n0007 : STD_LOGIC; 
  signal Min2_inst_cy_5 : STD_LOGIC; 
  signal CHOICE22 : STD_LOGIC; 
  signal N438 : STD_LOGIC; 
  signal Min2_inst_cy_7 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal Min1_0_ENABLE : STD_LOGIC; 
  signal Min1_0_TORGTS : STD_LOGIC; 
  signal Min1_0_OUTMUX : STD_LOGIC; 
  signal Min1_1_ENABLE : STD_LOGIC; 
  signal Min1_1_TORGTS : STD_LOGIC; 
  signal Min1_1_OUTMUX : STD_LOGIC; 
  signal Min1_2_ENABLE : STD_LOGIC; 
  signal Min1_2_TORGTS : STD_LOGIC; 
  signal Min1_2_OUTMUX : STD_LOGIC; 
  signal Min1_3_ENABLE : STD_LOGIC; 
  signal Min1_3_TORGTS : STD_LOGIC; 
  signal Min1_3_OUTMUX : STD_LOGIC; 
  signal Min2_0_ENABLE : STD_LOGIC; 
  signal Min2_0_TORGTS : STD_LOGIC; 
  signal Min2_0_OUTMUX : STD_LOGIC; 
  signal Min2_1_ENABLE : STD_LOGIC; 
  signal Min2_1_TORGTS : STD_LOGIC; 
  signal Min2_1_OUTMUX : STD_LOGIC; 
  signal Min2_2_ENABLE : STD_LOGIC; 
  signal Min2_2_TORGTS : STD_LOGIC; 
  signal Min2_2_OUTMUX : STD_LOGIC; 
  signal Min2_3_ENABLE : STD_LOGIC; 
  signal Min2_3_TORGTS : STD_LOGIC; 
  signal Min2_3_OUTMUX : STD_LOGIC; 
  signal reset_IBUF_0 : STD_LOGIC; 
  signal Enmin_ENABLE : STD_LOGIC; 
  signal Enmin_TORGTS : STD_LOGIC; 
  signal Enmin_OUTMUX : STD_LOGIC; 
  signal Enmin_OBUF : STD_LOGIC; 
  signal Enmin_OD : STD_LOGIC; 
  signal Enmin_SRMUXNOT : STD_LOGIC; 
  signal Madd_n0010_inst_lut2_01_O : STD_LOGIC; 
  signal Q_n0010_1_CYMUXG : STD_LOGIC; 
  signal Q_n0010_1_XORG : STD_LOGIC; 
  signal Q_n0010_1_GROM : STD_LOGIC; 
  signal Madd_n0010_inst_cy_0 : STD_LOGIC; 
  signal Q_n0010_1_LOGIC_ZERO : STD_LOGIC; 
  signal Q_n0010_2_LOGIC_ZERO : STD_LOGIC; 
  signal Q_n0010_2_FROM : STD_LOGIC; 
  signal Q_n0010_2_XORF : STD_LOGIC; 
  signal Q_n0010_2_XORG : STD_LOGIC; 
  signal Min1_3_rt : STD_LOGIC; 
  signal Madd_n0010_inst_cy_2 : STD_LOGIC; 
  signal Q_n0010_2_CYINIT : STD_LOGIC; 
  signal Min2_0_FROM : STD_LOGIC; 
  signal Min2_0_CYMUXG : STD_LOGIC; 
  signal Min2_inst_lut3_01_O : STD_LOGIC; 
  signal Min2_inst_cy_4 : STD_LOGIC; 
  signal Min2_0_LOGIC_ZERO : STD_LOGIC; 
  signal Min2_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Min2_inst_sum_4 : STD_LOGIC; 
  signal Min2_1_FROM : STD_LOGIC; 
  signal Min2_inst_sum_5 : STD_LOGIC; 
  signal Min2_1_CYMUXG : STD_LOGIC; 
  signal Min2_1_LOGIC_ZERO : STD_LOGIC; 
  signal Min2_inst_lut3_21_O : STD_LOGIC; 
  signal Min2_inst_cy_6 : STD_LOGIC; 
  signal Min2_1_CYINIT : STD_LOGIC; 
  signal Min2_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Min2_inst_sum_6 : STD_LOGIC; 
  signal Min2_3_rt : STD_LOGIC; 
  signal Min2_inst_sum_7 : STD_LOGIC; 
  signal Min2_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Min2_3_CYINIT : STD_LOGIC; 
  signal Min1_2_FROM : STD_LOGIC; 
  signal Min1_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Q_n0003_2_1_O : STD_LOGIC; 
  signal Min1_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Q_n0003_3_1_O : STD_LOGIC; 
  signal Min1_0_BXMUXNOT : STD_LOGIC; 
  signal Min1_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Q_n0003_1_1_O : STD_LOGIC; 
  signal CHOICE22_GROM : STD_LOGIC; 
  signal Q_n0007_GROM : STD_LOGIC; 
  signal Enmin_OFF_RST : STD_LOGIC; 
  signal Min2_0_FFY_RST : STD_LOGIC; 
  signal Min2_1_FFY_RST : STD_LOGIC; 
  signal Min2_1_FFX_RST : STD_LOGIC; 
  signal Min2_3_FFX_RST : STD_LOGIC; 
  signal Min1_2_FFY_RST : STD_LOGIC; 
  signal Min1_3_FFY_RST : STD_LOGIC; 
  signal Min1_0_FFY_RST : STD_LOGIC; 
  signal Min1_0_FFX_RST : STD_LOGIC; 
  signal clkm_BUFGP_BUFG_CE : STD_LOGIC; 
  signal PWR_GND_0_FROM : STD_LOGIC; 
  signal PWR_GND_0_GROM : STD_LOGIC; 
  signal PWR_GND_1_GROM : STD_LOGIC; 
  signal PWR_VCC_0_FROM : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal Q_n0010 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
begin
  Min1_0_OBUF : X_TRI
    port map (
      I => Min1_0_OUTMUX,
      CTL => Min1_0_ENABLE,
      O => Min1(0)
    );
  Min1_0_ENABLEINV : X_INV
    port map (
      I => Min1_0_TORGTS,
      O => Min1_0_ENABLE
    );
  Min1_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Min1_0_TORGTS
    );
  Min1_0_OUTMUX_1 : X_BUF
    port map (
      I => Min1_0,
      O => Min1_0_OUTMUX
    );
  Min1_1_OBUF : X_TRI
    port map (
      I => Min1_1_OUTMUX,
      CTL => Min1_1_ENABLE,
      O => Min1(1)
    );
  Min1_1_ENABLEINV : X_INV
    port map (
      I => Min1_1_TORGTS,
      O => Min1_1_ENABLE
    );
  Min1_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Min1_1_TORGTS
    );
  Min1_1_OUTMUX_2 : X_BUF
    port map (
      I => Min1_1,
      O => Min1_1_OUTMUX
    );
  Min1_2_OBUF : X_TRI
    port map (
      I => Min1_2_OUTMUX,
      CTL => Min1_2_ENABLE,
      O => Min1(2)
    );
  Min1_2_ENABLEINV : X_INV
    port map (
      I => Min1_2_TORGTS,
      O => Min1_2_ENABLE
    );
  Min1_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Min1_2_TORGTS
    );
  Min1_2_OUTMUX_3 : X_BUF
    port map (
      I => Min1_2,
      O => Min1_2_OUTMUX
    );
  Min1_3_OBUF : X_TRI
    port map (
      I => Min1_3_OUTMUX,
      CTL => Min1_3_ENABLE,
      O => Min1(3)
    );
  Min1_3_ENABLEINV : X_INV
    port map (
      I => Min1_3_TORGTS,
      O => Min1_3_ENABLE
    );
  Min1_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Min1_3_TORGTS
    );
  Min1_3_OUTMUX_4 : X_BUF
    port map (
      I => Min1_3,
      O => Min1_3_OUTMUX
    );
  Min2_0_OBUF : X_TRI
    port map (
      I => Min2_0_OUTMUX,
      CTL => Min2_0_ENABLE,
      O => Min2(0)
    );
  Min2_0_ENABLEINV : X_INV
    port map (
      I => Min2_0_TORGTS,
      O => Min2_0_ENABLE
    );
  Min2_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Min2_0_TORGTS
    );
  Min2_0_OUTMUX_5 : X_BUF
    port map (
      I => Min2_0,
      O => Min2_0_OUTMUX
    );
  Min2_1_OBUF : X_TRI
    port map (
      I => Min2_1_OUTMUX,
      CTL => Min2_1_ENABLE,
      O => Min2(1)
    );
  Min2_1_ENABLEINV : X_INV
    port map (
      I => Min2_1_TORGTS,
      O => Min2_1_ENABLE
    );
  Min2_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Min2_1_TORGTS
    );
  Min2_1_OUTMUX_6 : X_BUF
    port map (
      I => Min2_1,
      O => Min2_1_OUTMUX
    );
  Min2_2_OBUF : X_TRI
    port map (
      I => Min2_2_OUTMUX,
      CTL => Min2_2_ENABLE,
      O => Min2(2)
    );
  Min2_2_ENABLEINV : X_INV
    port map (
      I => Min2_2_TORGTS,
      O => Min2_2_ENABLE
    );
  Min2_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Min2_2_TORGTS
    );
  Min2_2_OUTMUX_7 : X_BUF
    port map (
      I => Min2_2,
      O => Min2_2_OUTMUX
    );
  Min2_3_OBUF : X_TRI
    port map (
      I => Min2_3_OUTMUX,
      CTL => Min2_3_ENABLE,
      O => Min2(3)
    );
  Min2_3_ENABLEINV : X_INV
    port map (
      I => Min2_3_TORGTS,
      O => Min2_3_ENABLE
    );
  Min2_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Min2_3_TORGTS
    );
  Min2_3_OUTMUX_8 : X_BUF
    port map (
      I => Min2_3,
      O => Min2_3_OUTMUX
    );
  reset_IMUX : X_BUF
    port map (
      I => reset_IBUF_0,
      O => reset_IBUF
    );
  reset_IBUF_9 : X_BUF
    port map (
      I => reset,
      O => reset_IBUF_0
    );
  Enmin_OBUF_10 : X_TRI
    port map (
      I => Enmin_OUTMUX,
      CTL => Enmin_ENABLE,
      O => Enmin
    );
  Enmin_ENABLEINV : X_INV
    port map (
      I => Enmin_TORGTS,
      O => Enmin_ENABLE
    );
  Enmin_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Enmin_TORGTS
    );
  Enmin_OUTMUX_11 : X_BUF
    port map (
      I => Enmin_OBUF,
      O => Enmin_OUTMUX
    );
  Enmin_OMUX : X_BUF
    port map (
      I => Q_n0004_SW113_O,
      O => Enmin_OD
    );
  Enmin_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => Enmin_SRMUXNOT
    );
  Q_n0010_1_LOGIC_ZERO_12 : X_ZERO
    port map (
      O => Q_n0010_1_LOGIC_ZERO
    );
  Madd_n0010_inst_cy_0_13 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => Q_n0010_1_LOGIC_ZERO,
      SEL => Madd_n0010_inst_lut2_01_O,
      O => Madd_n0010_inst_cy_0
    );
  Madd_n0010_inst_lut2_01 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Min1_0,
      O => Madd_n0010_inst_lut2_01_O
    );
  Q_n0010_1_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Min1_1,
      O => Q_n0010_1_GROM
    );
  Q_n0010_1_COUTUSED : X_BUF
    port map (
      I => Q_n0010_1_CYMUXG,
      O => Madd_n0010_inst_cy_1
    );
  Q_n0010_1_YUSED : X_BUF
    port map (
      I => Q_n0010_1_XORG,
      O => Q_n0010(1)
    );
  Madd_n0010_inst_cy_1_14 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_0,
      IB => Madd_n0010_inst_cy_0,
      SEL => Q_n0010_1_GROM,
      O => Q_n0010_1_CYMUXG
    );
  Madd_n0010_inst_sum_1 : X_XOR2
    port map (
      I0 => Madd_n0010_inst_cy_0,
      I1 => Q_n0010_1_GROM,
      O => Q_n0010_1_XORG
    );
  Q_n0010_2_LOGIC_ZERO_15 : X_ZERO
    port map (
      O => Q_n0010_2_LOGIC_ZERO
    );
  Madd_n0010_inst_cy_2_16 : X_MUX2
    port map (
      IA => Q_n0010_2_LOGIC_ZERO,
      IB => Q_n0010_2_CYINIT,
      SEL => Q_n0010_2_FROM,
      O => Madd_n0010_inst_cy_2
    );
  Madd_n0010_inst_sum_2 : X_XOR2
    port map (
      I0 => Q_n0010_2_CYINIT,
      I1 => Q_n0010_2_FROM,
      O => Q_n0010_2_XORF
    );
  Q_n0010_2_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => Min1_2,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_n0010_2_FROM
    );
  Min1_3_rt_17 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Min1_3,
      O => Min1_3_rt
    );
  Q_n0010_2_XUSED : X_BUF
    port map (
      I => Q_n0010_2_XORF,
      O => Q_n0010(2)
    );
  Q_n0010_2_YUSED : X_BUF
    port map (
      I => Q_n0010_2_XORG,
      O => Q_n0010(3)
    );
  Madd_n0010_inst_sum_3 : X_XOR2
    port map (
      I0 => Madd_n0010_inst_cy_2,
      I1 => Min1_3_rt,
      O => Q_n0010_2_XORG
    );
  Q_n0010_2_CYINIT_18 : X_BUF
    port map (
      I => Madd_n0010_inst_cy_1,
      O => Q_n0010_2_CYINIT
    );
  Min2_0_LOGIC_ZERO_19 : X_ZERO
    port map (
      O => Min2_0_LOGIC_ZERO
    );
  Min2_inst_cy_4_20 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1_0,
      IB => Min2_0_LOGIC_ZERO,
      SEL => Min2_0_FROM,
      O => Min2_inst_cy_4
    );
  Q_n0004_SW113 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1_0,
      ADR1 => N438,