b.ant

EDA课程设计（带完整设计报告）

-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 11:36:11 2008

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY b IS
END b;

ARCHITECTURE testbench_arch OF b IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "f:\vhdl\shuzizhong\shuzizhong\b.ano";
	COMPONENT minute1
		PORT (
			clkm : In  std_logic;
			reset : In  std_logic;
			Min1 : Buffer  std_logic_vector (3 DOWNTO 0);
			Min2 : Buffer  std_logic_vector (3 DOWNTO 0);
			Enmin : Out  std_logic
		);
	END COMPONENT;

	SIGNAL clkm : std_logic;
	SIGNAL reset : std_logic;
	SIGNAL Min1 : std_logic_vector (3 DOWNTO 0);
	SIGNAL Min2 : std_logic_vector (3 DOWNTO 0);
	SIGNAL Enmin : std_logic;

BEGIN
	UUT : minute1
	PORT MAP (
		clkm => clkm,
		reset => reset,
		Min1 => Min1,
		Min2 => Min2,
		Enmin => Enmin
	);

	PROCESS -- clock process for clkm,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_Enmin(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Enmin,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Enmin);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_Min1(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Min1,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Min1);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_Min2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Min2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Min2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clkm <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clkm <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_Enmin(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clkm <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clkm
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		reset <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=200 ns
		reset <= transport '1';
		-- --------------------
		WAIT FOR 6060 ns; -- Time=6260 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION minute1_cfg OF b IS
	FOR testbench_arch
	END FOR;
END minute1_cfg;