topclock.syr

EDA课程设计（带完整设计报告）

#      32-bit up counter           : 1
#      4-bit up counter            : 3
# Adders/Subtractors               : 3
#      4-bit adder                 : 3

Cell Usage :
# BELS                             : 243
#      GND                         : 1
#      LUT1                        : 17
#      LUT2                        : 10
#      LUT2_L                      : 3
#      LUT3                        : 9
#      LUT3_L                      : 6
#      LUT4                        : 58
#      LUT4_D                      : 8
#      LUT4_L                      : 24
#      MUXCY                       : 53
#      VCC                         : 1
#      XORCY                       : 53
# FlipFlops/Latches                : 59
#      FDC                         : 14
#      FDCE                        : 1
#      FDCPE                       : 12
#      FDE                         : 32
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 68
#      IBUF                        : 1
#      OBUF                        : 67
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-6 

 Number of Slices:                      81  out of   2352     3%  
 Number of Slice Flip Flops:            59  out of   4704     1%  
 Number of 4 input LUTs:               135  out of   4704     2%  
 Number of bonded IOBs:                 68  out of    144    47%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 33    |
uo_clks:Q                          | NONE                   | 9     |
u1_Ensec:Q                         | NONE                   | 9     |
u2_Enmin:Q                         | NONE                   | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 11.654ns (Maximum Frequency: 85.807MHz)
   Minimum input arrival time before clock: 5.172ns
   Maximum output required time after clock: 12.755ns
   Maximum combinational path delay: 12.122ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               11.654ns (Levels of Logic = 10)
  Source:            uo_cnt_12 (FF)
  Destination:       uo_cnt_31 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: uo_cnt_12 to uo_cnt_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.085   1.206  uo_cnt_12 (uo_cnt_12)
     LUT4:I0->O            2   0.549   1.206  uo__n000199 (CHOICE368)
     LUT4:I1->O           13   0.549   2.250  uo__n0001149 (CHOICE385)
     LUT4_D:I3->O          7   0.549   1.755  uo__n0001165 (uo__n0001)
     LUT3_L:I0->LO         1   0.549   0.000  uo_cnt_inst_lut3_261 (uo_cnt_inst_lut3_26)
     MUXCY:S->O            1   0.659   0.000  uo_cnt_inst_cy_27 (uo_cnt_inst_cy_27)
     MUXCY:CI->O           1   0.042   0.000  uo_cnt_inst_cy_28 (uo_cnt_inst_cy_28)
     MUXCY:CI->O           1   0.042   0.000  uo_cnt_inst_cy_29 (uo_cnt_inst_cy_29)
     MUXCY:CI->O           1   0.042   0.000  uo_cnt_inst_cy_30 (uo_cnt_inst_cy_30)
     MUXCY:CI->O           0   0.042   0.000  uo_cnt_inst_cy_31 (uo_cnt_inst_cy_31)
     XORCY:CI->O           1   0.420   0.000  uo_cnt_inst_sum_31 (uo_cnt_inst_sum_31)
     FDE:D                     0.709          uo_cnt_31
    ----------------------------------------
    Total                     11.654ns (5.237ns logic, 6.417ns route)
                                       (44.9% logic, 55.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'uo_clks:Q'
Delay:               7.922ns (Levels of Logic = 7)
  Source:            u1_Sec1_0 (FF)
  Destination:       u1_sec2_35 (FF)
  Source Clock:      uo_clks:Q rising
  Destination Clock: uo_clks:Q rising

  Data Path: u1_Sec1_0 to u1_sec2_35
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             12   1.085   2.160  u1_Sec1_0 (u1_Sec1_0)
     LUT4:I2->O            6   0.549   1.665  u1_Ker32431 (u1_N3245)
     LUT2:I0->O            2   0.549   0.000  u1__n0004_SW113 (u1__n0004)
     MUXCY:S->O            1   0.659   0.000  u1_sec2_inst_cy_37 (u1_sec2_inst_cy_37)
     MUXCY:CI->O           1   0.042   0.000  u1_sec2_inst_cy_38 (u1_sec2_inst_cy_38)
     MUXCY:CI->O           1   0.042   0.000  u1_sec2_inst_cy_39 (u1_sec2_inst_cy_39)
     MUXCY:CI->O           0   0.042   0.000  u1_sec2_inst_cy_40 (u1_sec2_inst_cy_40)
     XORCY:CI->O           1   0.420   0.000  u1_sec2_inst_sum_39 (u1_sec2_inst_sum_39)
     FDCPE:D                   0.709          u1_sec2_35
    ----------------------------------------
    Total                      7.922ns (4.097ns logic, 3.825ns route)
                                       (51.7% logic, 48.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u1_Ensec:Q'
Delay:               8.012ns (Levels of Logic = 7)
  Source:            u2_Min1_0 (FF)
  Destination:       u2_Min2_35 (FF)
  Source Clock:      u1_Ensec:Q rising
  Destination Clock: u1_Ensec:Q rising

  Data Path: u2_Min1_0 to u2_Min2_35
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   1.085   2.250  u2_Min1_0 (u2_Min1_0)
     LUT4:I2->O            6   0.549   1.665  u2_Ker34381 (u2_N3440)
     LUT2:I0->O            2   0.549   0.000  u2__n0004_SW113 (u2__n0004)
     MUXCY:S->O            1   0.659   0.000  u2_Min2_inst_cy_37 (u2_Min2_inst_cy_37)
     MUXCY:CI->O           1   0.042   0.000  u2_Min2_inst_cy_38 (u2_Min2_inst_cy_38)
     MUXCY:CI->O           1   0.042   0.000  u2_Min2_inst_cy_39 (u2_Min2_inst_cy_39)
     MUXCY:CI->O           0   0.042   0.000  u2_Min2_inst_cy_40 (u2_Min2_inst_cy_40)
     XORCY:CI->O           1   0.420   0.000  u2_Min2_inst_sum_39 (u2_Min2_inst_sum_39)
     FDCPE:D                   0.709          u2_Min2_35
    ----------------------------------------
    Total                      8.012ns (4.097ns logic, 3.915ns route)
                                       (51.1% logic, 48.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u2_Enmin:Q'
Delay:               8.229ns (Levels of Logic = 3)
  Source:            u3_Hou1_0 (FF)
  Destination:       u3_Hou1_2 (FF)
  Source Clock:      u2_Enmin:Q rising
  Destination Clock: u2_Enmin:Q rising

  Data Path: u3_Hou1_0 to u3_Hou1_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   1.085   2.250  u3_Hou1_0 (u3_Hou1_0)
     LUT4_D:I2->O          3   0.549   1.332  u3__n00038 (CHOICE323)
     LUT4_D:I0->O          2   0.549   1.206  u3__n0010 (u3__n0010)
     LUT2_L:I0->LO         1   0.549   0.000  u3__n0002<2>1 (u3__n0002<2>)
     FDC:D                     0.709          u3_Hou1_2
    ----------------------------------------
    Total                      8.229ns (3.441ns logic, 4.788ns route)
                                       (41.8% logic, 58.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              5.172ns (Levels of Logic = 1)
  Source:            reset (PAD)
  Destination:       uo_cnt_28 (FF)
  Destination Clock: clk rising

  Data Path: reset to uo_cnt_28
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            34   0.776   3.510  reset_IBUF (reset_IBUF)
     FDE:CE                    0.886          uo_cnt_0
    ----------------------------------------
    Total                      5.172ns (1.662ns logic, 3.510ns route)
                                       (32.1% logic, 67.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u1_Ensec:Q'
Offset:              12.755ns (Levels of Logic = 4)
  Source:            u2_Min1_0 (FF)
  Destination:       Alarm (PAD)
  Source Clock:      u1_Ensec:Q rising

  Data Path: u2_Min1_0 to Alarm
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   1.085   2.250  u2_Min1_0 (u2_Min1_0)
     LUT3:I0->O            1   0.549   1.035  u5_Alarm10 (CHOICE295)
     LUT4:I3->O            1   0.549   1.035  u5_Alarm16_SW0 (N7492)
     LUT4:I3->O            1   0.549   1.035  u5_Alarm16 (Alarm_OBUF)
     OBUF:I->O                 4.668          Alarm_OBUF (Alarm)
    ----------------------------------------
    Total                     12.755ns (7.400ns logic, 5.355ns route)
                                       (58.0% logic, 42.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u2_Enmin:Q'
Offset:              9.587ns (Levels of Logic = 2)
  Source:            u3_Hou1_0 (FF)
  Destination:       h1<6> (PAD)
  Source Clock:      u2_Enmin:Q rising

  Data Path: u3_Hou1_0 to h1<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   1.085   2.250  u3_Hou1_0 (u3_Hou1_0)
     LUT4:I2->O            1   0.549   1.035  u4_h1<1>1 (h1_1_OBUF)
     OBUF:I->O                 4.668          h1_1_OBUF (h1<1>)
    ----------------------------------------
    Total                      9.587ns (6.302ns logic, 3.285ns route)
                                       (65.7% logic, 34.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'uo_clks:Q'
Offset:              9.497ns (Levels of Logic = 2)
  Source:            u1_Sec1_0 (FF)
  Destination:       s1<6> (PAD)
  Source Clock:      uo_clks:Q rising

  Data Path: u1_Sec1_0 to s1<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             12   1.085   2.160  u1_Sec1_0 (u1_Sec1_0)
     LUT4:I2->O            1   0.549   1.035  u4_s1<1>1 (s1_1_OBUF)
     OBUF:I->O                 4.668          s1_1_OBUF (s1<1>)
    ----------------------------------------
    Total                      9.497ns (6.302ns logic, 3.195ns route)
                                       (66.4% logic, 33.6% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               12.122ns (Levels of Logic = 4)
  Source:            reset (PAD)
  Destination:       Alarm (PAD)

  Data Path: reset to Alarm
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            34   0.776   3.510  reset_IBUF (reset_IBUF)
     LUT4:I1->O            1   0.549   1.035  u5_Alarm16_SW0 (N7492)
     LUT4:I3->O            1   0.549   1.035  u5_Alarm16 (Alarm_OBUF)
     OBUF:I->O                 4.668          Alarm_OBUF (Alarm)
    ----------------------------------------
    Total                     12.122ns (6.542ns logic, 5.580ns route)
                                       (54.0% logic, 46.0% route)

=========================================================================
CPU : 3.91 / 4.81 s | Elapsed : 4.00 / 5.00 s
 
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Total memory usage is 63336 kilobytes