topclock.syr

EDA课程设计（带完整设计报告）

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: topclock.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : topclock.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : topclock
Output Format                      : NGC
Target Device                      : xc2s200-6-pq208

---- Source Options
Top Module Name                    : topclock
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : topclock.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/chenyi/shuzizhong/jhgjgh.vhdl in Library work.
Architecture behavioral of Entity jhgjgh is up to date.
Compiling vhdl file D:/chenyi/shuzizhong/second.vhdl in Library work.
Architecture a of Entity second1 is up to date.
Compiling vhdl file D:/chenyi/shuzizhong/minute.vhdl in Library work.
Architecture a of Entity minute1 is up to date.
Compiling vhdl file D:/chenyi/shuzizhong/hour1.vhdl in Library work.
Architecture a of Entity hour1 is up to date.
Compiling vhdl file D:/chenyi/shuzizhong/yima.vhdl in Library work.
Entity <yima> (Architecture <aaaa>) compiled.
Compiling vhdl file D:/chenyi/shuzizhong/alm.vhdl in Library work.
Architecture a of Entity alarm1 is up to date.
Compiling vhdl file D:/chenyi/shuzizhong/main.vhdl in Library work.
Architecture one of Entity topclock is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <topclock> (Architecture <one>).
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 10: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 10: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 10: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 10: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 10: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 10: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 8: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 8: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 8: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 8: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 8: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - D:/chenyi/shuzizhong/main.vhdl line 8: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <topclock> analyzed. Unit <topclock> generated.

Analyzing Entity <jhgjgh> (Architecture <behavioral>).
Entity <jhgjgh> analyzed. Unit <jhgjgh> generated.

Analyzing Entity <second1> (Architecture <a>).
Entity <second1> analyzed. Unit <second1> generated.

Analyzing Entity <minute1> (Architecture <a>).
Entity <minute1> analyzed. Unit <minute1> generated.

Analyzing Entity <hour1> (Architecture <a>).
Entity <hour1> analyzed. Unit <hour1> generated.

Analyzing Entity <yima> (Architecture <aaaa>).
Entity <yima> analyzed. Unit <yima> generated.

Analyzing Entity <alarm1> (Architecture <a>).
Entity <alarm1> analyzed. Unit <alarm1> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <alarm1>.
    Related source file is D:/chenyi/shuzizhong/alm.vhdl.
Unit <alarm1> synthesized.


Synthesizing Unit <yima>.
    Related source file is D:/chenyi/shuzizhong/yima.vhdl.
Unit <yima> synthesized.


Synthesizing Unit <hour1>.
    Related source file is D:/chenyi/shuzizhong/hour1.vhdl.
    Found 4-bit register for signal <Hou1>.
    Found 4-bit up counter for signal <hou2>.
    Found 4-bit adder for signal <$n0009> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   4 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <hour1> synthesized.


Synthesizing Unit <minute1>.
    Related source file is D:/chenyi/shuzizhong/minute.vhdl.
    Found 1-bit register for signal <Enmin>.
    Found 4-bit register for signal <Min1>.
    Found 4-bit up counter for signal <Min2>.
    Found 4-bit adder for signal <$n0010> created at line 30.
    Summary:
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <minute1> synthesized.


Synthesizing Unit <second1>.
    Related source file is D:/chenyi/shuzizhong/second.vhdl.
    Found 4-bit register for signal <Sec1>.
    Found 4-bit up counter for signal <sec2>.
    Found 1-bit register for signal <Ensec>.
    Found 4-bit adder for signal <$n0010> created at line 30.
    Summary:
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <second1> synthesized.


Synthesizing Unit <jhgjgh>.
    Related source file is D:/chenyi/shuzizhong/jhgjgh.vhdl.
    Found 1-bit register for signal <clks>.
    Found 32-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jhgjgh> synthesized.


Synthesizing Unit <topclock>.
    Related source file is D:/chenyi/shuzizhong/main.vhdl.
Unit <topclock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 3
 4-bit adder                       : 3
# Counters                         : 4
 32-bit up counter                 : 1
 4-bit up counter                  : 3
# Registers                        : 6
 1-bit register                    : 3
 4-bit register                    : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <topclock> ...

Optimizing unit <yima> ...

Optimizing unit <jhgjgh> ...

Optimizing unit <second1> ...

Optimizing unit <minute1> ...

Optimizing unit <hour1> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topclock, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : topclock.ngr
Top Level Output File Name         : topclock
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 69

Macro Statistics :
# Registers                        : 6
#      1-bit register              : 3
#      4-bit register              : 3
# Counters                         : 4