topclock.par

EDA课程设计（带完整设计报告）

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

LENOVO-4690ABD7::  Sun Dec 07 15:45:10 2008


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 topclock_map.ncd
topclock.ncd topclock.pcf 


Constraints file: topclock.pcf

Loading device database for application Par from file "topclock_map.ncd".
   "topclock" is an NCD, version 2.38, device xc2s200, package pq208, speed -6
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <Alarm> must be placed at site P136.
Resolved that IOB <s1<0>> must be placed at site P101.
Resolved that IOB <s1<1>> must be placed at site P102.
Resolved that IOB <s1<2>> must be placed at site P108.
Resolved that IOB <m1<0>> must be placed at site P83.
Resolved that IOB <s1<3>> must be placed at site P109.
Resolved that IOB <m1<1>> must be placed at site P84.
Resolved that IOB <s2<0>> must be placed at site P94.
Resolved that IOB <s1<4>> must be placed at site P110.
Resolved that GCLKIOB <clk> must be placed at site P182.
Resolved that IOB <m1<2>> must be placed at site P86.
Resolved that IOB <s2<1>> must be placed at site P95.
Resolved that IOB <s1<5>> must be placed at site P111.
Resolved that IOB <m1<3>> must be placed at site P87.
Resolved that IOB <s2<2>> must be placed at site P96.
Resolved that IOB <s1<6>> must be placed at site P112.
Resolved that IOB <m2<0>> must be placed at site P70.
Resolved that IOB <m1<4>> must be placed at site P88.
Resolved that IOB <s2<3>> must be placed at site P97.
Resolved that IOB <m2<1>> must be placed at site P71.
Resolved that IOB <m1<5>> must be placed at site P89.
Resolved that IOB <s2<4>> must be placed at site P98.
Resolved that IOB <m2<2>> must be placed at site P73.
Resolved that IOB <m1<6>> must be placed at site P90.
Resolved that IOB <s2<5>> must be placed at site P99.
Resolved that IOB <m2<3>> must be placed at site P74.
Resolved that IOB <s2<6>> must be placed at site P100.
Resolved that IOB <m2<4>> must be placed at site P75.
Resolved that IOB <m2<5>> must be placed at site P81.
Resolved that IOB <m2<6>> must be placed at site P82.
Resolved that IOB <h1<0>> must be placed at site P60.
Resolved that IOB <h1<1>> must be placed at site P61.
Resolved that IOB <h1<2>> must be placed at site P62.
Resolved that IOB <h1<3>> must be placed at site P63.
Resolved that IOB <h2<0>> must be placed at site P46.
Resolved that IOB <h1<4>> must be placed at site P67.
Resolved that IOB <h2<1>> must be placed at site P47.
Resolved that IOB <h1<5>> must be placed at site P68.
Resolved that IOB <h2<2>> must be placed at site P48.
Resolved that IOB <h1<6>> must be placed at site P69.
Resolved that IOB <h2<3>> must be placed at site P49.
Resolved that IOB <h2<4>> must be placed at site P57.
Resolved that IOB <h2<5>> must be placed at site P58.
Resolved that IOB <h2<6>> must be placed at site P59.
Resolved that IOB <reset> must be placed at site P121.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            68 out of 140    48%
      Number of LOCed External IOBs   44 out of 68     64%

   Number of SLICEs                   79 out of 2352    3%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9899e3) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9ac323) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file topclock.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 643 unrouted;       REAL time: 0 secs 

Phase 2: 597 unrouted;       REAL time: 12 secs 

Phase 3: 157 unrouted;       REAL time: 12 secs 

Phase 4: 0 unrouted;       REAL time: 12 secs 

Total REAL time to Router completion: 12 secs 
Total CPU time to Router completion: 12 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   18   |  0.073     |  0.560      |
+----------------------------+----------+--------+------------+-------------+
|          u1_Ensec          |Low-Skew  |    6   |  0.358     |  5.151      |
+----------------------------+----------+--------+------------+-------------+
|          u2_Enmin          |   Local  |    6   |  1.025     |  3.243      |
+----------------------------+----------+--------+------------+-------------+
|           uo_clks          |   Local  |    7   |  0.105     |  3.227      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 194


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.352
   The MAXIMUM PIN DELAY IS:                               5.151
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.927

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
         250         291          74          22           6           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 13 secs 
Total CPU time to PAR completion: 12 secs 

Peak Memory Usage:  65 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file topclock.ncd.


PAR done.