topclock_timesim.vhd

EDA课程设计（带完整设计报告）

      SEL => u2_Min2_inst_lut3_21_O,
      O => u2_Min2_1_CYMUXG
    );
  u2_Min2_inst_sum_6_127 : X_XOR2
    port map (
      I0 => u2_Min2_inst_cy_6,
      I1 => u2_Min2_inst_lut3_21_O,
      O => u2_Min2_inst_sum_6
    );
  u2_Min2_1_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => u2_Min2_1_SRMUX_OUTPUTNOT
    );
  u2_Min2_1_CYINIT_128 : X_BUF
    port map (
      I => u2_Min2_inst_cy_5,
      O => u2_Min2_1_CYINIT
    );
  u2_Min2_3_FFX_RSTOR : X_OR2
    port map (
      I0 => u2_Min2_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => u2_Min2_3_FFX_RST
    );
  u2_Min2_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u2_Min2_inst_sum_7,
      CE => u2_n0007,
      CLK => u1_Ensec,
      SET => GND,
      RST => u2_Min2_3_FFX_RST,
      O => u2_Min2(3)
    );
  u2_Min2_inst_sum_7_129 : X_XOR2
    port map (
      I0 => u2_Min2_3_CYINIT,
      I1 => u2_Min2_3_rt,
      O => u2_Min2_inst_sum_7
    );
  u2_Min2_3_rt_130 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => u2_Min2(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => u2_Min2_3_rt
    );
  u2_Min2_3_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => u2_Min2_3_SRMUX_OUTPUTNOT
    );
  u2_Min2_3_CYINIT_131 : X_BUF
    port map (
      I => u2_Min2_inst_cy_7,
      O => u2_Min2_3_CYINIT
    );
  u2_n0010_1_LOGIC_ZERO_132 : X_ZERO
    port map (
      O => u2_n0010_1_LOGIC_ZERO
    );
  u2_Madd_n0010_inst_cy_0_133 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1_1,
      IB => u2_n0010_1_LOGIC_ZERO,
      SEL => u2_Madd_n0010_inst_lut2_01_O,
      O => u2_Madd_n0010_inst_cy_0
    );
  u2_Madd_n0010_inst_lut2_01 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1_1,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u2_Min1(0),
      O => u2_Madd_n0010_inst_lut2_01_O
    );
  u2_n0010_1_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_1,
      ADR1 => VCC,
      ADR2 => u2_Min1(1),
      ADR3 => VCC,
      O => u2_n0010_1_GROM
    );
  u2_n0010_1_COUTUSED : X_BUF
    port map (
      I => u2_n0010_1_CYMUXG,
      O => u2_Madd_n0010_inst_cy_1
    );
  u2_n0010_1_YUSED : X_BUF
    port map (
      I => u2_n0010_1_XORG,
      O => u2_n0010(1)
    );
  u2_Madd_n0010_inst_cy_1_134 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_1,
      IB => u2_Madd_n0010_inst_cy_0,
      SEL => u2_n0010_1_GROM,
      O => u2_n0010_1_CYMUXG
    );
  u2_Madd_n0010_inst_sum_1 : X_XOR2
    port map (
      I0 => u2_Madd_n0010_inst_cy_0,
      I1 => u2_n0010_1_GROM,
      O => u2_n0010_1_XORG
    );
  u2_n0010_2_LOGIC_ZERO_135 : X_ZERO
    port map (
      O => u2_n0010_2_LOGIC_ZERO
    );
  u2_Madd_n0010_inst_cy_2_136 : X_MUX2
    port map (
      IA => u2_n0010_2_LOGIC_ZERO,
      IB => u2_n0010_2_CYINIT,
      SEL => u2_n0010_2_FROM,
      O => u2_Madd_n0010_inst_cy_2
    );
  u2_Madd_n0010_inst_sum_2 : X_XOR2
    port map (
      I0 => u2_n0010_2_CYINIT,
      I1 => u2_n0010_2_FROM,
      O => u2_n0010_2_XORF
    );
  u2_n0010_2_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u2_Min1(2),
      ADR3 => VCC,
      O => u2_n0010_2_FROM
    );
  u2_Min1_3_rt_137 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u2_Min1(3),
      O => u2_Min1_3_rt
    );
  u2_n0010_2_XUSED : X_BUF
    port map (
      I => u2_n0010_2_XORF,
      O => u2_n0010(2)
    );
  u2_n0010_2_YUSED : X_BUF
    port map (
      I => u2_n0010_2_XORG,
      O => u2_n0010(3)
    );
  u2_Madd_n0010_inst_sum_3 : X_XOR2
    port map (
      I0 => u2_Madd_n0010_inst_cy_2,
      I1 => u2_Min1_3_rt,
      O => u2_n0010_2_XORG
    );
  u2_n0010_2_CYINIT_138 : X_BUF
    port map (
      I => u2_Madd_n0010_inst_cy_1,
      O => u2_n0010_2_CYINIT
    );
  u1_Ensec_LOGIC_ZERO_139 : X_ZERO
    port map (
      O => u1_Ensec_LOGIC_ZERO
    );
  u1_sec2_inst_cy_4_140 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1_0,
      IB => u1_Ensec_LOGIC_ZERO,
      SEL => u1_n0004_SW113_O,
      O => u1_sec2_inst_cy_4
    );
  u1_n0004_SW113 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1_0,
      ADR1 => u1_N2334,
      ADR2 => VCC,
      ADR3 => CHOICE197,
      O => u1_n0004_SW113_O
    );
  u1_sec2_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"CF00"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_0,
      ADR1 => u1_N2334,
      ADR2 => CHOICE197,
      ADR3 => u1_sec2(0),
      O => u1_sec2_inst_lut3_01_O
    );
  u1_Ensec_COUTUSED : X_BUF
    port map (
      I => u1_Ensec_CYMUXG,
      O => u1_sec2_inst_cy_5
    );
  u1_Ensec_YUSED : X_BUF
    port map (
      I => u1_Ensec_XORG,
      O => u1_sec2_inst_sum_4
    );
  u1_sec2_inst_cy_5_141 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_0,
      IB => u1_sec2_inst_cy_4,
      SEL => u1_sec2_inst_lut3_01_O,
      O => u1_Ensec_CYMUXG
    );
  u1_sec2_inst_sum_4_142 : X_XOR2
    port map (
      I0 => u1_sec2_inst_cy_4,
      I1 => u1_sec2_inst_lut3_01_O,
      O => u1_Ensec_XORG
    );
  u1_Ensec_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => u1_Ensec_SRMUX_OUTPUTNOT
    );
  u1_sec2_1_FFY_RSTOR : X_OR2
    port map (
      I0 => u1_sec2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => u1_sec2_1_FFY_RST
    );
  u1_sec2_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u1_sec2_inst_sum_6,
      CE => u1_n0007,
      CLK => clk_BUFGP,
      SET => GND,
      RST => u1_sec2_1_FFY_RST,
      O => u1_sec2(2)
    );
  u1_sec2_1_LOGIC_ZERO_143 : X_ZERO
    port map (
      O => u1_sec2_1_LOGIC_ZERO
    );
  u1_sec2_inst_cy_6_144 : X_MUX2
    port map (
      IA => u1_sec2_1_LOGIC_ZERO,
      IB => u1_sec2_1_CYINIT,
      SEL => u1_sec2_1_FROM,
      O => u1_sec2_inst_cy_6
    );
  u1_sec2_inst_sum_5_145 : X_XOR2
    port map (
      I0 => u1_sec2_1_CYINIT,
      I1 => u1_sec2_1_FROM,
      O => u1_sec2_inst_sum_5
    );
  u1_sec2_1_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u1_sec2(1),
      O => u1_sec2_1_FROM
    );
  u1_sec2_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"B0B0"
    )
    port map (
      ADR0 => u1_N2334,
      ADR1 => CHOICE197,
      ADR2 => u1_sec2(2),
      ADR3 => VCC,
      O => u1_sec2_inst_lut3_21_O
    );
  u1_sec2_1_COUTUSED : X_BUF
    port map (
      I => u1_sec2_1_CYMUXG,
      O => u1_sec2_inst_cy_7
    );
  u1_sec2_inst_cy_7_146 : X_MUX2
    port map (
      IA => u1_sec2_1_LOGIC_ZERO,
      IB => u1_sec2_inst_cy_6,
      SEL => u1_sec2_inst_lut3_21_O,
      O => u1_sec2_1_CYMUXG
    );
  u1_sec2_inst_sum_6_147 : X_XOR2
    port map (
      I0 => u1_sec2_inst_cy_6,
      I1 => u1_sec2_inst_lut3_21_O,
      O => u1_sec2_inst_sum_6
    );
  u1_sec2_1_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => u1_sec2_1_SRMUX_OUTPUTNOT
    );
  u1_sec2_1_CYINIT_148 : X_BUF
    port map (
      I => u1_sec2_inst_cy_5,
      O => u1_sec2_1_CYINIT
    );
  u1_sec2_inst_sum_7_149 : X_XOR2
    port map (
      I0 => u1_sec2_3_CYINIT,
      I1 => u1_sec2_3_rt,
      O => u1_sec2_inst_sum_7
    );
  u1_sec2_3_rt_150 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u1_sec2(3),
      O => u1_sec2_3_rt
    );
  u1_sec2_3_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => u1_sec2_3_SRMUX_OUTPUTNOT
    );
  u1_sec2_3_CYINIT_151 : X_BUF
    port map (
      I => u1_sec2_inst_cy_7,
      O => u1_sec2_3_CYINIT
    );
  u1_n0010_1_LOGIC_ZERO_152 : X_ZERO
    port map (
      O => u1_n0010_1_LOGIC_ZERO
    );
  u1_Madd_n0010_inst_cy_0_153 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => u1_n0010_1_LOGIC_ZERO,
      SEL => u1_Madd_n0010_inst_lut2_01_O,
      O => u1_Madd_n0010_inst_cy_0
    );
  u1_Madd_n0010_inst_lut2_01 : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => u1_Sec1(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => u1_Madd_n0010_inst_lut2_01_O
    );
  u1_n0010_1_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => u1_Sec1(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => u1_n0010_1_GROM
    );
  u1_n0010_1_COUTUSED : X_BUF
    port map (
      I => u1_n0010_1_CYMUXG,
      O => u1_Madd_n0010_inst_cy_1
    );
  u1_n0010_1_YUSED : X_BUF
    port map (
      I => u1_n0010_1_XORG,
      O => u1_n0010(1)
    );
  u1_Madd_n0010_inst_cy_1_154 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => u1_Madd_n0010_inst_cy_0,
      SEL => u1_n0010_1_GROM,
      O => u1_n0010_1_CYMUXG
    );
  u1_Madd_n0010_inst_sum_1 : X_XOR2
    port map (
      I0 => u1_Madd_n0010_inst_cy_0,
      I1 => u1_n0010_1_GROM,
      O => u1_n0010_1_XORG
    );
  u1_n0010_2_LOGIC_ZERO_155 : X_ZERO
    port map (
      O => u1_n0010_2_LOGIC_ZERO
    );
  u1_Madd_n0010_inst_cy_2_156 : X_MUX2
    port map (
      IA => u1_n0010_2_LOGIC_ZERO,
      IB => u1_n0010_2_CYINIT,
      SEL => u1_n0010_2_FROM,
      O => u1_Madd_n0010_inst_cy_2
    );
  u1_Madd_n0010_inst_sum_2 : X_XOR2
    port map (
      I0 => u1_n0010_2_CYINIT,
      I1 => u1_n0010_2_FROM,
      O => u1_n0010_2_XORF
    );
  u1_n0010_2_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u1_Sec1(2),
      ADR3 => VCC,
      O => u1_n0010_2_FROM
    );
  u1_Sec1_3_rt_157 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => u1_Sec1(3),
      ADR3 => VCC,
      O => u1_Sec1_3_rt
    );
  u1_n0010_2_XUSED : X_BUF
    port map (
      I => u1_n0010_2_XORF,
      O => u1_n0010(2)
    );
  u1_n0010_2_YUSED : X_BUF
    port map (
      I => u1_n0010_2_XORG,
      O => u1_n0010(3)
    );
  u1_Madd_n0010_inst_sum_3 : X_XOR2
    port map (
      I0 => u1_Madd_n0010_inst_cy_2,
      I1 => u1_Sec1_3_rt,
      O => u1_n0010_2_XORG
    );
  u1_n0010_2_CYINIT_158 : X_BUF
    port map (
      I => u1_Madd_n0010_inst_cy_1,
      O => u1_n0010_2_CYINIT
    );
  u3_hou2_0_FFY_RSTOR : X_OR2
    port map (
      I0 => u3_hou2_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => u3_hou2_0_FFY_RST
    );
  u3_hou2_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u3_hou2_inst_sum_4,
      CE => u3_n0011,
      CLK => u2_Enmin,
      SET => GND,
      RST => u3_hou2_0_FFY_RST,
      O => u3_hou2(0)
    );
  u3_hou2_0_LOGIC_ZERO_159 : X_ZERO
    port map (
      O => u3_hou2_0_LOGIC_ZERO
    );
  u3_hou2_inst_cy_4_160 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1_4,
      IB => u3_hou2_0_LOGIC_ZERO,
      SEL => u3_hou2_0_FROM,
      O => u3_hou2_inst_cy_4
    );
  u3_n000321 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1_4,
      ADR1 => CHOICE217,
      ADR2 => CHOICE211,
      ADR3 => VCC,
      O => u3_hou2_0_FROM
    );
  u3_hou2_0_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_4,
      ADR1 => VCC,
      ADR2 => u3_hou2(0),
      ADR3 => VCC,
      O => u3_hou2_0_GROM
    );
  u3_hou2_0_COUTUSED : X_BUF
    port map (
      I => u3_hou2_0_CYMUXG,
      O => u3_hou2_inst_cy_5
    );
  u3_hou2_0_XUSED : X_BUF
    port map (
      I => u3_hou2_0_FROM,
      O => u3_n0003
    );
  u3_hou2_inst_cy_5_161 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_4,
      IB => u3_hou2_inst_cy_4,
      SEL => u3_hou2_0_GROM,
      O => u3_hou2_0_CYMUXG
    );
  u3_hou2_inst_sum_4_162 : X_XOR2
    port map (
      I0 => u3_hou2_inst_cy_4,
      I1 => u3_hou2_0_GROM,
      O => u3_hou2_inst_sum_4
    );
  u3_hou2_0_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => u3_hou2_0_SRMUX_OUTPUTNOT
    );
  u3_hou2_1_FFX_RSTOR : X_OR2
    port map (
      I0 => u3_hou2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => u3_hou2_1_FFX_RST
    );
  u3_hou2_1 : X_FF
    generic map(