topclock_timesim.vhd

EDA课程设计（带完整设计报告）

    );
  sec2_2_ENABLEINV : X_INV
    port map (
      I => sec2_2_TORGTS,
      O => sec2_2_ENABLE
    );
  sec2_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sec2_2_TORGTS
    );
  sec2_2_OUTMUX_97 : X_BUF
    port map (
      I => u1_sec2(2),
      O => sec2_2_OUTMUX
    );
  hou2_0_OBUF : X_TRI
    port map (
      I => hou2_0_OUTMUX,
      CTL => hou2_0_ENABLE,
      O => hou2(0)
    );
  hou2_0_ENABLEINV : X_INV
    port map (
      I => hou2_0_TORGTS,
      O => hou2_0_ENABLE
    );
  hou2_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hou2_0_TORGTS
    );
  hou2_0_OUTMUX_98 : X_BUF
    port map (
      I => u3_hou2(0),
      O => hou2_0_OUTMUX
    );
  sec2_3_OBUF : X_TRI
    port map (
      I => sec2_3_OUTMUX,
      CTL => sec2_3_ENABLE,
      O => sec2(3)
    );
  sec2_3_ENABLEINV : X_INV
    port map (
      I => sec2_3_TORGTS,
      O => sec2_3_ENABLE
    );
  sec2_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sec2_3_TORGTS
    );
  sec2_3_OUTMUX_99 : X_BUF
    port map (
      I => u1_sec2(3),
      O => sec2_3_OUTMUX
    );
  hou2_1_OBUF : X_TRI
    port map (
      I => hou2_1_OUTMUX,
      CTL => hou2_1_ENABLE,
      O => hou2(1)
    );
  hou2_1_ENABLEINV : X_INV
    port map (
      I => hou2_1_TORGTS,
      O => hou2_1_ENABLE
    );
  hou2_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hou2_1_TORGTS
    );
  hou2_1_OUTMUX_100 : X_BUF
    port map (
      I => u3_hou2(1),
      O => hou2_1_OUTMUX
    );
  hou2_2_OBUF : X_TRI
    port map (
      I => hou2_2_OUTMUX,
      CTL => hou2_2_ENABLE,
      O => hou2(2)
    );
  hou2_2_ENABLEINV : X_INV
    port map (
      I => hou2_2_TORGTS,
      O => hou2_2_ENABLE
    );
  hou2_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hou2_2_TORGTS
    );
  hou2_2_OUTMUX_101 : X_BUF
    port map (
      I => u3_hou2(2),
      O => hou2_2_OUTMUX
    );
  hou2_3_OBUF : X_TRI
    port map (
      I => hou2_3_OUTMUX,
      CTL => hou2_3_ENABLE,
      O => hou2(3)
    );
  hou2_3_ENABLEINV : X_INV
    port map (
      I => hou2_3_TORGTS,
      O => hou2_3_ENABLE
    );
  hou2_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hou2_3_TORGTS
    );
  hou2_3_OUTMUX_102 : X_BUF
    port map (
      I => u3_hou2(3),
      O => hou2_3_OUTMUX
    );
  min1_0_OBUF : X_TRI
    port map (
      I => min1_0_OUTMUX,
      CTL => min1_0_ENABLE,
      O => min1(0)
    );
  min1_0_ENABLEINV : X_INV
    port map (
      I => min1_0_TORGTS,
      O => min1_0_ENABLE
    );
  min1_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => min1_0_TORGTS
    );
  min1_0_OUTMUX_103 : X_BUF
    port map (
      I => u2_Min1(0),
      O => min1_0_OUTMUX
    );
  min1_1_OBUF : X_TRI
    port map (
      I => min1_1_OUTMUX,
      CTL => min1_1_ENABLE,
      O => min1(1)
    );
  min1_1_ENABLEINV : X_INV
    port map (
      I => min1_1_TORGTS,
      O => min1_1_ENABLE
    );
  min1_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => min1_1_TORGTS
    );
  min1_1_OUTMUX_104 : X_BUF
    port map (
      I => u2_Min1(1),
      O => min1_1_OUTMUX
    );
  min1_2_OBUF : X_TRI
    port map (
      I => min1_2_OUTMUX,
      CTL => min1_2_ENABLE,
      O => min1(2)
    );
  min1_2_ENABLEINV : X_INV
    port map (
      I => min1_2_TORGTS,
      O => min1_2_ENABLE
    );
  min1_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => min1_2_TORGTS
    );
  min1_2_OUTMUX_105 : X_BUF
    port map (
      I => u2_Min1(2),
      O => min1_2_OUTMUX
    );
  min1_3_OBUF : X_TRI
    port map (
      I => min1_3_OUTMUX,
      CTL => min1_3_ENABLE,
      O => min1(3)
    );
  min1_3_ENABLEINV : X_INV
    port map (
      I => min1_3_TORGTS,
      O => min1_3_ENABLE
    );
  min1_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => min1_3_TORGTS
    );
  min1_3_OUTMUX_106 : X_BUF
    port map (
      I => u2_Min1(3),
      O => min1_3_OUTMUX
    );
  min2_0_OBUF : X_TRI
    port map (
      I => min2_0_OUTMUX,
      CTL => min2_0_ENABLE,
      O => min2(0)
    );
  min2_0_ENABLEINV : X_INV
    port map (
      I => min2_0_TORGTS,
      O => min2_0_ENABLE
    );
  min2_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => min2_0_TORGTS
    );
  min2_0_OUTMUX_107 : X_BUF
    port map (
      I => u2_Min2(0),
      O => min2_0_OUTMUX
    );
  min2_1_OBUF : X_TRI
    port map (
      I => min2_1_OUTMUX,
      CTL => min2_1_ENABLE,
      O => min2(1)
    );
  min2_1_ENABLEINV : X_INV
    port map (
      I => min2_1_TORGTS,
      O => min2_1_ENABLE
    );
  min2_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => min2_1_TORGTS
    );
  min2_1_OUTMUX_108 : X_BUF
    port map (
      I => u2_Min2(1),
      O => min2_1_OUTMUX
    );
  min2_2_OBUF : X_TRI
    port map (
      I => min2_2_OUTMUX,
      CTL => min2_2_ENABLE,
      O => min2(2)
    );
  min2_2_ENABLEINV : X_INV
    port map (
      I => min2_2_TORGTS,
      O => min2_2_ENABLE
    );
  min2_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => min2_2_TORGTS
    );
  min2_2_OUTMUX_109 : X_BUF
    port map (
      I => u2_Min2(2),
      O => min2_2_OUTMUX
    );
  min2_3_OBUF : X_TRI
    port map (
      I => min2_3_OUTMUX,
      CTL => min2_3_ENABLE,
      O => min2(3)
    );
  min2_3_ENABLEINV : X_INV
    port map (
      I => min2_3_TORGTS,
      O => min2_3_ENABLE
    );
  min2_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => min2_3_TORGTS
    );
  min2_3_OUTMUX_110 : X_BUF
    port map (
      I => u2_Min2(3),
      O => min2_3_OUTMUX
    );
  reset_IMUX : X_BUF
    port map (
      I => reset_IBUF_0,
      O => reset_IBUF
    );
  reset_IBUF_111 : X_BUF
    port map (
      I => reset,
      O => reset_IBUF_0
    );
  u3_n0009_1_LOGIC_ZERO_112 : X_ZERO
    port map (
      O => u3_n0009_1_LOGIC_ZERO
    );
  u3_Madd_n0009_inst_cy_0_113 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1_3,
      IB => u3_n0009_1_LOGIC_ZERO,
      SEL => u3_Madd_n0009_inst_lut2_01_O,
      O => u3_Madd_n0009_inst_cy_0
    );
  u3_Madd_n0009_inst_lut2_01 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1_3,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u3_Hou1(0),
      O => u3_Madd_n0009_inst_lut2_01_O
    );
  u3_n0009_1_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_3,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u3_Hou1(1),
      O => u3_n0009_1_GROM
    );
  u3_n0009_1_COUTUSED : X_BUF
    port map (
      I => u3_n0009_1_CYMUXG,
      O => u3_Madd_n0009_inst_cy_1
    );
  u3_n0009_1_YUSED : X_BUF
    port map (
      I => u3_n0009_1_XORG,
      O => u3_n0009(1)
    );
  u3_Madd_n0009_inst_cy_1_114 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_3,
      IB => u3_Madd_n0009_inst_cy_0,
      SEL => u3_n0009_1_GROM,
      O => u3_n0009_1_CYMUXG
    );
  u3_Madd_n0009_inst_sum_1 : X_XOR2
    port map (
      I0 => u3_Madd_n0009_inst_cy_0,
      I1 => u3_n0009_1_GROM,
      O => u3_n0009_1_XORG
    );
  u3_n0009_2_LOGIC_ZERO_115 : X_ZERO
    port map (
      O => u3_n0009_2_LOGIC_ZERO
    );
  u3_Madd_n0009_inst_cy_2_116 : X_MUX2
    port map (
      IA => u3_n0009_2_LOGIC_ZERO,
      IB => u3_n0009_2_CYINIT,
      SEL => u3_n0009_2_FROM,
      O => u3_Madd_n0009_inst_cy_2
    );
  u3_Madd_n0009_inst_sum_2 : X_XOR2
    port map (
      I0 => u3_n0009_2_CYINIT,
      I1 => u3_n0009_2_FROM,
      O => u3_n0009_2_XORF
    );
  u3_n0009_2_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => u3_Hou1(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => u3_n0009_2_FROM
    );
  u3_Hou1_3_rt_117 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => u3_Hou1(3),
      O => u3_Hou1_3_rt
    );
  u3_n0009_2_XUSED : X_BUF
    port map (
      I => u3_n0009_2_XORF,
      O => u3_n0009(2)
    );
  u3_n0009_2_YUSED : X_BUF
    port map (
      I => u3_n0009_2_XORG,
      O => u3_n0009(3)
    );
  u3_Madd_n0009_inst_sum_3 : X_XOR2
    port map (
      I0 => u3_Madd_n0009_inst_cy_2,
      I1 => u3_Hou1_3_rt,
      O => u3_n0009_2_XORG
    );
  u3_n0009_2_CYINIT_118 : X_BUF
    port map (
      I => u3_Madd_n0009_inst_cy_1,
      O => u3_n0009_2_CYINIT
    );
  u2_Enmin_LOGIC_ZERO_119 : X_ZERO
    port map (
      O => u2_Enmin_LOGIC_ZERO
    );
  u2_Min2_inst_cy_4_120 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1_2,
      IB => u2_Enmin_LOGIC_ZERO,
      SEL => u2_n0004_SW113_O,
      O => u2_Min2_inst_cy_4
    );
  u2_n0004_SW113 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1_2,
      ADR1 => CHOICE204,
      ADR2 => VCC,
      ADR3 => u2_N2529,
      O => u2_n0004_SW113_O
    );
  u2_Min2_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"F030"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0_2,
      ADR1 => CHOICE204,
      ADR2 => u2_Min2(0),
      ADR3 => u2_N2529,
      O => u2_Min2_inst_lut3_01_O
    );
  u2_Enmin_COUTUSED : X_BUF
    port map (
      I => u2_Enmin_CYMUXG,
      O => u2_Min2_inst_cy_5
    );
  u2_Enmin_YUSED : X_BUF
    port map (
      I => u2_Enmin_XORG,
      O => u2_Min2_inst_sum_4
    );
  u2_Min2_inst_cy_5_121 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0_2,
      IB => u2_Min2_inst_cy_4,
      SEL => u2_Min2_inst_lut3_01_O,
      O => u2_Enmin_CYMUXG
    );
  u2_Min2_inst_sum_4_122 : X_XOR2
    port map (
      I0 => u2_Min2_inst_cy_4,
      I1 => u2_Min2_inst_lut3_01_O,
      O => u2_Enmin_XORG
    );
  u2_Enmin_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => u2_Enmin_SRMUX_OUTPUTNOT
    );
  u2_Min2_1_FFY_RSTOR : X_OR2
    port map (
      I0 => u2_Min2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => u2_Min2_1_FFY_RST
    );
  u2_Min2_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u2_Min2_inst_sum_6,
      CE => u2_n0007,
      CLK => u1_Ensec,
      SET => GND,
      RST => u2_Min2_1_FFY_RST,
      O => u2_Min2(2)
    );
  u2_Min2_1_FFX_RSTOR : X_OR2
    port map (
      I0 => u2_Min2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => u2_Min2_1_FFX_RST
    );
  u2_Min2_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => u2_Min2_inst_sum_5,
      CE => u2_n0007,
      CLK => u1_Ensec,
      SET => GND,
      RST => u2_Min2_1_FFX_RST,
      O => u2_Min2(1)
    );
  u2_Min2_1_LOGIC_ZERO_123 : X_ZERO
    port map (
      O => u2_Min2_1_LOGIC_ZERO
    );
  u2_Min2_inst_cy_6_124 : X_MUX2
    port map (
      IA => u2_Min2_1_LOGIC_ZERO,
      IB => u2_Min2_1_CYINIT,
      SEL => u2_Min2_1_FROM,
      O => u2_Min2_inst_cy_6
    );
  u2_Min2_inst_sum_5_125 : X_XOR2
    port map (
      I0 => u2_Min2_1_CYINIT,
      I1 => u2_Min2_1_FROM,
      O => u2_Min2_inst_sum_5
    );
  u2_Min2_1_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => u2_Min2(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => u2_Min2_1_FROM
    );
  u2_Min2_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"CF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => u2_N2529,
      ADR2 => CHOICE204,
      ADR3 => u2_Min2(2),
      O => u2_Min2_inst_lut3_21_O
    );
  u2_Min2_1_COUTUSED : X_BUF
    port map (
      I => u2_Min2_1_CYMUXG,
      O => u2_Min2_inst_cy_7
    );
  u2_Min2_inst_cy_7_126 : X_MUX2
    port map (
      IA => u2_Min2_1_LOGIC_ZERO,
      IB => u2_Min2_inst_cy_6,