topclock_timesim.vhd

EDA课程设计（带完整设计报告）

    port map (
      I => GTS,
      O => m1_6_TORGTS
    );
  m1_6_OUTMUX_50 : X_BUF
    port map (
      I => m1_6_OBUF,
      O => m1_6_OUTMUX
    );
  s2_5_OBUF_51 : X_TRI
    port map (
      I => s2_5_OUTMUX,
      CTL => s2_5_ENABLE,
      O => s2(5)
    );
  s2_5_ENABLEINV : X_INV
    port map (
      I => s2_5_TORGTS,
      O => s2_5_ENABLE
    );
  s2_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s2_5_TORGTS
    );
  s2_5_OUTMUX_52 : X_BUF
    port map (
      I => s2_5_OBUF,
      O => s2_5_OUTMUX
    );
  m2_3_OBUF_53 : X_TRI
    port map (
      I => m2_3_OUTMUX,
      CTL => m2_3_ENABLE,
      O => m2(3)
    );
  m2_3_ENABLEINV : X_INV
    port map (
      I => m2_3_TORGTS,
      O => m2_3_ENABLE
    );
  m2_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m2_3_TORGTS
    );
  m2_3_OUTMUX_54 : X_BUF
    port map (
      I => m2_3_OBUF,
      O => m2_3_OUTMUX
    );
  s2_6_OBUF_55 : X_TRI
    port map (
      I => s2_6_OUTMUX,
      CTL => s2_6_ENABLE,
      O => s2(6)
    );
  s2_6_ENABLEINV : X_INV
    port map (
      I => s2_6_TORGTS,
      O => s2_6_ENABLE
    );
  s2_6_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s2_6_TORGTS
    );
  s2_6_OUTMUX_56 : X_BUF
    port map (
      I => s2_6_OBUF,
      O => s2_6_OUTMUX
    );
  m2_4_OBUF_57 : X_TRI
    port map (
      I => m2_4_OUTMUX,
      CTL => m2_4_ENABLE,
      O => m2(4)
    );
  m2_4_ENABLEINV : X_INV
    port map (
      I => m2_4_TORGTS,
      O => m2_4_ENABLE
    );
  m2_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m2_4_TORGTS
    );
  m2_4_OUTMUX_58 : X_BUF
    port map (
      I => m2_4_OBUF,
      O => m2_4_OUTMUX
    );
  m2_5_OBUF_59 : X_TRI
    port map (
      I => m2_5_OUTMUX,
      CTL => m2_5_ENABLE,
      O => m2(5)
    );
  m2_5_ENABLEINV : X_INV
    port map (
      I => m2_5_TORGTS,
      O => m2_5_ENABLE
    );
  m2_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m2_5_TORGTS
    );
  m2_5_OUTMUX_60 : X_BUF
    port map (
      I => m2_5_OBUF,
      O => m2_5_OUTMUX
    );
  m2_6_OBUF_61 : X_TRI
    port map (
      I => m2_6_OUTMUX,
      CTL => m2_6_ENABLE,
      O => m2(6)
    );
  m2_6_ENABLEINV : X_INV
    port map (
      I => m2_6_TORGTS,
      O => m2_6_ENABLE
    );
  m2_6_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m2_6_TORGTS
    );
  m2_6_OUTMUX_62 : X_BUF
    port map (
      I => m2_6_OBUF,
      O => m2_6_OUTMUX
    );
  h1_0_OBUF_63 : X_TRI
    port map (
      I => h1_0_OUTMUX,
      CTL => h1_0_ENABLE,
      O => h1(0)
    );
  h1_0_ENABLEINV : X_INV
    port map (
      I => h1_0_TORGTS,
      O => h1_0_ENABLE
    );
  h1_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h1_0_TORGTS
    );
  h1_0_OUTMUX_64 : X_BUF
    port map (
      I => h1_0_OBUF,
      O => h1_0_OUTMUX
    );
  h1_1_OBUF_65 : X_TRI
    port map (
      I => h1_1_OUTMUX,
      CTL => h1_1_ENABLE,
      O => h1(1)
    );
  h1_1_ENABLEINV : X_INV
    port map (
      I => h1_1_TORGTS,
      O => h1_1_ENABLE
    );
  h1_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h1_1_TORGTS
    );
  h1_1_OUTMUX_66 : X_BUF
    port map (
      I => h1_1_OBUF,
      O => h1_1_OUTMUX
    );
  h1_2_OBUF_67 : X_TRI
    port map (
      I => h1_2_OUTMUX,
      CTL => h1_2_ENABLE,
      O => h1(2)
    );
  h1_2_ENABLEINV : X_INV
    port map (
      I => h1_2_TORGTS,
      O => h1_2_ENABLE
    );
  h1_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h1_2_TORGTS
    );
  h1_2_OUTMUX_68 : X_BUF
    port map (
      I => h1_2_OBUF,
      O => h1_2_OUTMUX
    );
  h1_3_OBUF_69 : X_TRI
    port map (
      I => h1_3_OUTMUX,
      CTL => h1_3_ENABLE,
      O => h1(3)
    );
  h1_3_ENABLEINV : X_INV
    port map (
      I => h1_3_TORGTS,
      O => h1_3_ENABLE
    );
  h1_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h1_3_TORGTS
    );
  h1_3_OUTMUX_70 : X_BUF
    port map (
      I => h1_3_OBUF,
      O => h1_3_OUTMUX
    );
  h2_0_OBUF_71 : X_TRI
    port map (
      I => h2_0_OUTMUX,
      CTL => h2_0_ENABLE,
      O => h2(0)
    );
  h2_0_ENABLEINV : X_INV
    port map (
      I => h2_0_TORGTS,
      O => h2_0_ENABLE
    );
  h2_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h2_0_TORGTS
    );
  h2_0_OUTMUX_72 : X_BUF
    port map (
      I => h2_0_OBUF,
      O => h2_0_OUTMUX
    );
  h1_4_OBUF_73 : X_TRI
    port map (
      I => h1_4_OUTMUX,
      CTL => h1_4_ENABLE,
      O => h1(4)
    );
  h1_4_ENABLEINV : X_INV
    port map (
      I => h1_4_TORGTS,
      O => h1_4_ENABLE
    );
  h1_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h1_4_TORGTS
    );
  h1_4_OUTMUX_74 : X_BUF
    port map (
      I => h1_4_OBUF,
      O => h1_4_OUTMUX
    );
  h2_1_OBUF_75 : X_TRI
    port map (
      I => h2_1_OUTMUX,
      CTL => h2_1_ENABLE,
      O => h2(1)
    );
  h2_1_ENABLEINV : X_INV
    port map (
      I => h2_1_TORGTS,
      O => h2_1_ENABLE
    );
  h2_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h2_1_TORGTS
    );
  h2_1_OUTMUX_76 : X_BUF
    port map (
      I => h2_1_OBUF,
      O => h2_1_OUTMUX
    );
  h1_5_OBUF_77 : X_TRI
    port map (
      I => h1_5_OUTMUX,
      CTL => h1_5_ENABLE,
      O => h1(5)
    );
  h1_5_ENABLEINV : X_INV
    port map (
      I => h1_5_TORGTS,
      O => h1_5_ENABLE
    );
  h1_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h1_5_TORGTS
    );
  h1_5_OUTMUX_78 : X_BUF
    port map (
      I => h1_5_OBUF,
      O => h1_5_OUTMUX
    );
  h2_2_OBUF_79 : X_TRI
    port map (
      I => h2_2_OUTMUX,
      CTL => h2_2_ENABLE,
      O => h2(2)
    );
  h2_2_ENABLEINV : X_INV
    port map (
      I => h2_2_TORGTS,
      O => h2_2_ENABLE
    );
  h2_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h2_2_TORGTS
    );
  h2_2_OUTMUX_80 : X_BUF
    port map (
      I => h2_2_OBUF,
      O => h2_2_OUTMUX
    );
  h1_6_OBUF_81 : X_TRI
    port map (
      I => h1_6_OUTMUX,
      CTL => h1_6_ENABLE,
      O => h1(6)
    );
  h1_6_ENABLEINV : X_INV
    port map (
      I => h1_6_TORGTS,
      O => h1_6_ENABLE
    );
  h1_6_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h1_6_TORGTS
    );
  h1_6_OUTMUX_82 : X_BUF
    port map (
      I => h1_6_OBUF,
      O => h1_6_OUTMUX
    );
  hou1_0_OBUF : X_TRI
    port map (
      I => hou1_0_OUTMUX,
      CTL => hou1_0_ENABLE,
      O => hou1(0)
    );
  hou1_0_ENABLEINV : X_INV
    port map (
      I => hou1_0_TORGTS,
      O => hou1_0_ENABLE
    );
  hou1_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hou1_0_TORGTS
    );
  hou1_0_OUTMUX_83 : X_BUF
    port map (
      I => u3_Hou1(0),
      O => hou1_0_OUTMUX
    );
  h2_3_OBUF_84 : X_TRI
    port map (
      I => h2_3_OUTMUX,
      CTL => h2_3_ENABLE,
      O => h2(3)
    );
  h2_3_ENABLEINV : X_INV
    port map (
      I => h2_3_TORGTS,
      O => h2_3_ENABLE
    );
  h2_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h2_3_TORGTS
    );
  h2_3_OUTMUX_85 : X_BUF
    port map (
      I => h2_3_OBUF,
      O => h2_3_OUTMUX
    );
  hou1_1_OBUF : X_TRI
    port map (
      I => hou1_1_OUTMUX,
      CTL => hou1_1_ENABLE,
      O => hou1(1)
    );
  hou1_1_ENABLEINV : X_INV
    port map (
      I => hou1_1_TORGTS,
      O => hou1_1_ENABLE
    );
  hou1_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hou1_1_TORGTS
    );
  hou1_1_OUTMUX_86 : X_BUF
    port map (
      I => u3_Hou1(1),
      O => hou1_1_OUTMUX
    );
  h2_4_OBUF_87 : X_TRI
    port map (
      I => h2_4_OUTMUX,
      CTL => h2_4_ENABLE,
      O => h2(4)
    );
  h2_4_ENABLEINV : X_INV
    port map (
      I => h2_4_TORGTS,
      O => h2_4_ENABLE
    );
  h2_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h2_4_TORGTS
    );
  h2_4_OUTMUX_88 : X_BUF
    port map (
      I => h2_4_OBUF,
      O => h2_4_OUTMUX
    );
  sec2_0_OBUF : X_TRI
    port map (
      I => sec2_0_OUTMUX,
      CTL => sec2_0_ENABLE,
      O => sec2(0)
    );
  sec2_0_ENABLEINV : X_INV
    port map (
      I => sec2_0_TORGTS,
      O => sec2_0_ENABLE
    );
  sec2_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sec2_0_TORGTS
    );
  sec2_0_OUTMUX_89 : X_BUF
    port map (
      I => u1_sec2(0),
      O => sec2_0_OUTMUX
    );
  hou1_2_OBUF : X_TRI
    port map (
      I => hou1_2_OUTMUX,
      CTL => hou1_2_ENABLE,
      O => hou1(2)
    );
  hou1_2_ENABLEINV : X_INV
    port map (
      I => hou1_2_TORGTS,
      O => hou1_2_ENABLE
    );
  hou1_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hou1_2_TORGTS
    );
  hou1_2_OUTMUX_90 : X_BUF
    port map (
      I => u3_Hou1(2),
      O => hou1_2_OUTMUX
    );
  h2_5_OBUF_91 : X_TRI
    port map (
      I => h2_5_OUTMUX,
      CTL => h2_5_ENABLE,
      O => h2(5)
    );
  h2_5_ENABLEINV : X_INV
    port map (
      I => h2_5_TORGTS,
      O => h2_5_ENABLE
    );
  h2_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h2_5_TORGTS
    );
  h2_5_OUTMUX_92 : X_BUF
    port map (
      I => h2_5_OBUF,
      O => h2_5_OUTMUX
    );
  sec2_1_OBUF : X_TRI
    port map (
      I => sec2_1_OUTMUX,
      CTL => sec2_1_ENABLE,
      O => sec2(1)
    );
  sec2_1_ENABLEINV : X_INV
    port map (
      I => sec2_1_TORGTS,
      O => sec2_1_ENABLE
    );
  sec2_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sec2_1_TORGTS
    );
  sec2_1_OUTMUX_93 : X_BUF
    port map (
      I => u1_sec2(1),
      O => sec2_1_OUTMUX
    );
  hou1_3_OBUF : X_TRI
    port map (
      I => hou1_3_OUTMUX,
      CTL => hou1_3_ENABLE,
      O => hou1(3)
    );
  hou1_3_ENABLEINV : X_INV
    port map (
      I => hou1_3_TORGTS,
      O => hou1_3_ENABLE
    );
  hou1_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hou1_3_TORGTS
    );
  hou1_3_OUTMUX_94 : X_BUF
    port map (
      I => u3_Hou1(3),
      O => hou1_3_OUTMUX
    );
  h2_6_OBUF_95 : X_TRI
    port map (
      I => h2_6_OUTMUX,
      CTL => h2_6_ENABLE,
      O => h2(6)
    );
  h2_6_ENABLEINV : X_INV
    port map (
      I => h2_6_TORGTS,
      O => h2_6_ENABLE
    );
  h2_6_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => h2_6_TORGTS
    );
  h2_6_OUTMUX_96 : X_BUF
    port map (
      I => h2_6_OBUF,
      O => h2_6_OUTMUX
    );
  sec2_2_OBUF : X_TRI
    port map (
      I => sec2_2_OUTMUX,
      CTL => sec2_2_ENABLE,
      O => sec2(2)