topclock_timesim.vhd

EDA课程设计（带完整设计报告）

  signal u1_n0010 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
begin
  Alarm_OBUF_1 : X_TRI
    port map (
      I => Alarm_OUTMUX,
      CTL => Alarm_ENABLE,
      O => Alarm
    );
  Alarm_ENABLEINV : X_INV
    port map (
      I => Alarm_TORGTS,
      O => Alarm_ENABLE
    );
  Alarm_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Alarm_TORGTS
    );
  Alarm_OUTMUX_2 : X_BUF
    port map (
      I => Alarm_OBUF,
      O => Alarm_OUTMUX
    );
  s1_0_OBUF_3 : X_TRI
    port map (
      I => s1_0_OUTMUX,
      CTL => s1_0_ENABLE,
      O => s1(0)
    );
  s1_0_ENABLEINV : X_INV
    port map (
      I => s1_0_TORGTS,
      O => s1_0_ENABLE
    );
  s1_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s1_0_TORGTS
    );
  s1_0_OUTMUX_4 : X_BUF
    port map (
      I => s1_0_OBUF,
      O => s1_0_OUTMUX
    );
  s1_1_OBUF_5 : X_TRI
    port map (
      I => s1_1_OUTMUX,
      CTL => s1_1_ENABLE,
      O => s1(1)
    );
  s1_1_ENABLEINV : X_INV
    port map (
      I => s1_1_TORGTS,
      O => s1_1_ENABLE
    );
  s1_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s1_1_TORGTS
    );
  s1_1_OUTMUX_6 : X_BUF
    port map (
      I => s1_1_OBUF,
      O => s1_1_OUTMUX
    );
  s1_2_OBUF_7 : X_TRI
    port map (
      I => s1_2_OUTMUX,
      CTL => s1_2_ENABLE,
      O => s1(2)
    );
  s1_2_ENABLEINV : X_INV
    port map (
      I => s1_2_TORGTS,
      O => s1_2_ENABLE
    );
  s1_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s1_2_TORGTS
    );
  s1_2_OUTMUX_8 : X_BUF
    port map (
      I => s1_2_OBUF,
      O => s1_2_OUTMUX
    );
  m1_0_OBUF_9 : X_TRI
    port map (
      I => m1_0_OUTMUX,
      CTL => m1_0_ENABLE,
      O => m1(0)
    );
  m1_0_ENABLEINV : X_INV
    port map (
      I => m1_0_TORGTS,
      O => m1_0_ENABLE
    );
  m1_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m1_0_TORGTS
    );
  m1_0_OUTMUX_10 : X_BUF
    port map (
      I => m1_0_OBUF,
      O => m1_0_OUTMUX
    );
  s1_3_OBUF_11 : X_TRI
    port map (
      I => s1_3_OUTMUX,
      CTL => s1_3_ENABLE,
      O => s1(3)
    );
  s1_3_ENABLEINV : X_INV
    port map (
      I => s1_3_TORGTS,
      O => s1_3_ENABLE
    );
  s1_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s1_3_TORGTS
    );
  s1_3_OUTMUX_12 : X_BUF
    port map (
      I => s1_3_OBUF,
      O => s1_3_OUTMUX
    );
  Sec1_0_OBUF : X_TRI
    port map (
      I => Sec1_0_OUTMUX,
      CTL => Sec1_0_ENABLE,
      O => Sec1(0)
    );
  Sec1_0_ENABLEINV : X_INV
    port map (
      I => Sec1_0_TORGTS,
      O => Sec1_0_ENABLE
    );
  Sec1_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Sec1_0_TORGTS
    );
  Sec1_0_OUTMUX_13 : X_BUF
    port map (
      I => u1_Sec1(0),
      O => Sec1_0_OUTMUX
    );
  m1_1_OBUF_14 : X_TRI
    port map (
      I => m1_1_OUTMUX,
      CTL => m1_1_ENABLE,
      O => m1(1)
    );
  m1_1_ENABLEINV : X_INV
    port map (
      I => m1_1_TORGTS,
      O => m1_1_ENABLE
    );
  m1_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m1_1_TORGTS
    );
  m1_1_OUTMUX_15 : X_BUF
    port map (
      I => m1_1_OBUF,
      O => m1_1_OUTMUX
    );
  s2_0_OBUF_16 : X_TRI
    port map (
      I => s2_0_OUTMUX,
      CTL => s2_0_ENABLE,
      O => s2(0)
    );
  s2_0_ENABLEINV : X_INV
    port map (
      I => s2_0_TORGTS,
      O => s2_0_ENABLE
    );
  s2_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s2_0_TORGTS
    );
  s2_0_OUTMUX_17 : X_BUF
    port map (
      I => s2_0_OBUF,
      O => s2_0_OUTMUX
    );
  s1_4_OBUF_18 : X_TRI
    port map (
      I => s1_4_OUTMUX,
      CTL => s1_4_ENABLE,
      O => s1(4)
    );
  s1_4_ENABLEINV : X_INV
    port map (
      I => s1_4_TORGTS,
      O => s1_4_ENABLE
    );
  s1_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s1_4_TORGTS
    );
  s1_4_OUTMUX_19 : X_BUF
    port map (
      I => s1_4_OBUF,
      O => s1_4_OUTMUX
    );
  Sec1_1_OBUF : X_TRI
    port map (
      I => Sec1_1_OUTMUX,
      CTL => Sec1_1_ENABLE,
      O => Sec1(1)
    );
  Sec1_1_ENABLEINV : X_INV
    port map (
      I => Sec1_1_TORGTS,
      O => Sec1_1_ENABLE
    );
  Sec1_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Sec1_1_TORGTS
    );
  Sec1_1_OUTMUX_20 : X_BUF
    port map (
      I => u1_Sec1(1),
      O => Sec1_1_OUTMUX
    );
  m1_2_OBUF_21 : X_TRI
    port map (
      I => m1_2_OUTMUX,
      CTL => m1_2_ENABLE,
      O => m1(2)
    );
  m1_2_ENABLEINV : X_INV
    port map (
      I => m1_2_TORGTS,
      O => m1_2_ENABLE
    );
  m1_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m1_2_TORGTS
    );
  m1_2_OUTMUX_22 : X_BUF
    port map (
      I => m1_2_OBUF,
      O => m1_2_OUTMUX
    );
  s2_1_OBUF_23 : X_TRI
    port map (
      I => s2_1_OUTMUX,
      CTL => s2_1_ENABLE,
      O => s2(1)
    );
  s2_1_ENABLEINV : X_INV
    port map (
      I => s2_1_TORGTS,
      O => s2_1_ENABLE
    );
  s2_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s2_1_TORGTS
    );
  s2_1_OUTMUX_24 : X_BUF
    port map (
      I => s2_1_OBUF,
      O => s2_1_OUTMUX
    );
  s1_5_OBUF_25 : X_TRI
    port map (
      I => s1_5_OUTMUX,
      CTL => s1_5_ENABLE,
      O => s1(5)
    );
  s1_5_ENABLEINV : X_INV
    port map (
      I => s1_5_TORGTS,
      O => s1_5_ENABLE
    );
  s1_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s1_5_TORGTS
    );
  s1_5_OUTMUX_26 : X_BUF
    port map (
      I => s1_5_OBUF,
      O => s1_5_OUTMUX
    );
  Sec1_2_OBUF : X_TRI
    port map (
      I => Sec1_2_OUTMUX,
      CTL => Sec1_2_ENABLE,
      O => Sec1(2)
    );
  Sec1_2_ENABLEINV : X_INV
    port map (
      I => Sec1_2_TORGTS,
      O => Sec1_2_ENABLE
    );
  Sec1_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Sec1_2_TORGTS
    );
  Sec1_2_OUTMUX_27 : X_BUF
    port map (
      I => u1_Sec1(2),
      O => Sec1_2_OUTMUX
    );
  m1_3_OBUF_28 : X_TRI
    port map (
      I => m1_3_OUTMUX,
      CTL => m1_3_ENABLE,
      O => m1(3)
    );
  m1_3_ENABLEINV : X_INV
    port map (
      I => m1_3_TORGTS,
      O => m1_3_ENABLE
    );
  m1_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m1_3_TORGTS
    );
  m1_3_OUTMUX_29 : X_BUF
    port map (
      I => m1_3_OBUF,
      O => m1_3_OUTMUX
    );
  s2_2_OBUF_30 : X_TRI
    port map (
      I => s2_2_OUTMUX,
      CTL => s2_2_ENABLE,
      O => s2(2)
    );
  s2_2_ENABLEINV : X_INV
    port map (
      I => s2_2_TORGTS,
      O => s2_2_ENABLE
    );
  s2_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s2_2_TORGTS
    );
  s2_2_OUTMUX_31 : X_BUF
    port map (
      I => s2_2_OBUF,
      O => s2_2_OUTMUX
    );
  s1_6_OBUF_32 : X_TRI
    port map (
      I => s1_6_OUTMUX,
      CTL => s1_6_ENABLE,
      O => s1(6)
    );
  s1_6_ENABLEINV : X_INV
    port map (
      I => s1_6_TORGTS,
      O => s1_6_ENABLE
    );
  s1_6_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s1_6_TORGTS
    );
  s1_6_OUTMUX_33 : X_BUF
    port map (
      I => s1_6_OBUF,
      O => s1_6_OUTMUX
    );
  Sec1_3_OBUF : X_TRI
    port map (
      I => Sec1_3_OUTMUX,
      CTL => Sec1_3_ENABLE,
      O => Sec1(3)
    );
  Sec1_3_ENABLEINV : X_INV
    port map (
      I => Sec1_3_TORGTS,
      O => Sec1_3_ENABLE
    );
  Sec1_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => Sec1_3_TORGTS
    );
  Sec1_3_OUTMUX_34 : X_BUF
    port map (
      I => u1_Sec1(3),
      O => Sec1_3_OUTMUX
    );
  m2_0_OBUF_35 : X_TRI
    port map (
      I => m2_0_OUTMUX,
      CTL => m2_0_ENABLE,
      O => m2(0)
    );
  m2_0_ENABLEINV : X_INV
    port map (
      I => m2_0_TORGTS,
      O => m2_0_ENABLE
    );
  m2_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m2_0_TORGTS
    );
  m2_0_OUTMUX_36 : X_BUF
    port map (
      I => m2_0_OBUF,
      O => m2_0_OUTMUX
    );
  m1_4_OBUF_37 : X_TRI
    port map (
      I => m1_4_OUTMUX,
      CTL => m1_4_ENABLE,
      O => m1(4)
    );
  m1_4_ENABLEINV : X_INV
    port map (
      I => m1_4_TORGTS,
      O => m1_4_ENABLE
    );
  m1_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m1_4_TORGTS
    );
  m1_4_OUTMUX_38 : X_BUF
    port map (
      I => m1_4_OBUF,
      O => m1_4_OUTMUX
    );
  s2_3_OBUF_39 : X_TRI
    port map (
      I => s2_3_OUTMUX,
      CTL => s2_3_ENABLE,
      O => s2(3)
    );
  s2_3_ENABLEINV : X_INV
    port map (
      I => s2_3_TORGTS,
      O => s2_3_ENABLE
    );
  s2_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s2_3_TORGTS
    );
  s2_3_OUTMUX_40 : X_BUF
    port map (
      I => s2_3_OBUF,
      O => s2_3_OUTMUX
    );
  m2_1_OBUF_41 : X_TRI
    port map (
      I => m2_1_OUTMUX,
      CTL => m2_1_ENABLE,
      O => m2(1)
    );
  m2_1_ENABLEINV : X_INV
    port map (
      I => m2_1_TORGTS,
      O => m2_1_ENABLE
    );
  m2_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m2_1_TORGTS
    );
  m2_1_OUTMUX_42 : X_BUF
    port map (
      I => m2_1_OBUF,
      O => m2_1_OUTMUX
    );
  m1_5_OBUF_43 : X_TRI
    port map (
      I => m1_5_OUTMUX,
      CTL => m1_5_ENABLE,
      O => m1(5)
    );
  m1_5_ENABLEINV : X_INV
    port map (
      I => m1_5_TORGTS,
      O => m1_5_ENABLE
    );
  m1_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m1_5_TORGTS
    );
  m1_5_OUTMUX_44 : X_BUF
    port map (
      I => m1_5_OBUF,
      O => m1_5_OUTMUX
    );
  s2_4_OBUF_45 : X_TRI
    port map (
      I => s2_4_OUTMUX,
      CTL => s2_4_ENABLE,
      O => s2(4)
    );
  s2_4_ENABLEINV : X_INV
    port map (
      I => s2_4_TORGTS,
      O => s2_4_ENABLE
    );
  s2_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => s2_4_TORGTS
    );
  s2_4_OUTMUX_46 : X_BUF
    port map (
      I => s2_4_OBUF,
      O => s2_4_OUTMUX
    );
  m2_2_OBUF_47 : X_TRI
    port map (
      I => m2_2_OUTMUX,
      CTL => m2_2_ENABLE,
      O => m2(2)
    );
  m2_2_ENABLEINV : X_INV
    port map (
      I => m2_2_TORGTS,
      O => m2_2_ENABLE
    );
  m2_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => m2_2_TORGTS
    );
  m2_2_OUTMUX_48 : X_BUF
    port map (
      I => m2_2_OBUF,
      O => m2_2_OUTMUX
    );
  m1_6_OBUF_49 : X_TRI
    port map (
      I => m1_6_OUTMUX,
      CTL => m1_6_ENABLE,
      O => m1(6)
    );
  m1_6_ENABLEINV : X_INV
    port map (
      I => m1_6_TORGTS,
      O => m1_6_ENABLE
    );
  m1_6_GTS_OR : X_BUF