topclock_timesim.vhd

EDA课程设计（带完整设计报告）

-- Xilinx Vhdl netlist produced by netgen application (version G.28)
-- Command       : -intstyle ise -s 6 -pcf topclock.pcf -ngm topclock.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim topclock.ncd topclock_timesim.vhd 
-- Input file    : topclock.ncd
-- Output file   : topclock_timesim.vhd
-- Design name   : topclock
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : 2s200pq208-6 (PRODUCTION 1.27 2003-12-13)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity topclock is
  port (
    Alarm : out STD_LOGIC; 
    reset : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    sec2 : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    Sec1 : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    min2 : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    min1 : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    s2 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    s1 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    hou2 : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    hou1 : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    m2 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    m1 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    h2 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    h1 : out STD_LOGIC_VECTOR ( 6 downto 0 ) 
  );
end topclock;

architecture Structure of topclock is
  signal Alarm_OBUF : STD_LOGIC; 
  signal s1_0_OBUF : STD_LOGIC; 
  signal s1_1_OBUF : STD_LOGIC; 
  signal s1_2_OBUF : STD_LOGIC; 
  signal m1_0_OBUF : STD_LOGIC; 
  signal s1_3_OBUF : STD_LOGIC; 
  signal m1_1_OBUF : STD_LOGIC; 
  signal s2_0_OBUF : STD_LOGIC; 
  signal s1_4_OBUF : STD_LOGIC; 
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal m1_2_OBUF : STD_LOGIC; 
  signal s2_1_OBUF : STD_LOGIC; 
  signal s1_5_OBUF : STD_LOGIC; 
  signal m1_3_OBUF : STD_LOGIC; 
  signal s2_2_OBUF : STD_LOGIC; 
  signal s1_6_OBUF : STD_LOGIC; 
  signal m2_0_OBUF : STD_LOGIC; 
  signal m1_4_OBUF : STD_LOGIC; 
  signal s2_3_OBUF : STD_LOGIC; 
  signal m2_1_OBUF : STD_LOGIC; 
  signal m1_5_OBUF : STD_LOGIC; 
  signal s2_4_OBUF : STD_LOGIC; 
  signal m2_2_OBUF : STD_LOGIC; 
  signal m1_6_OBUF : STD_LOGIC; 
  signal s2_5_OBUF : STD_LOGIC; 
  signal m2_3_OBUF : STD_LOGIC; 
  signal s2_6_OBUF : STD_LOGIC; 
  signal m2_4_OBUF : STD_LOGIC; 
  signal m2_5_OBUF : STD_LOGIC; 
  signal m2_6_OBUF : STD_LOGIC; 
  signal h1_0_OBUF : STD_LOGIC; 
  signal h1_1_OBUF : STD_LOGIC; 
  signal h1_2_OBUF : STD_LOGIC; 
  signal h1_3_OBUF : STD_LOGIC; 
  signal h2_0_OBUF : STD_LOGIC; 
  signal h1_4_OBUF : STD_LOGIC; 
  signal h2_1_OBUF : STD_LOGIC; 
  signal h1_5_OBUF : STD_LOGIC; 
  signal h2_2_OBUF : STD_LOGIC; 
  signal h1_6_OBUF : STD_LOGIC; 
  signal h2_3_OBUF : STD_LOGIC; 
  signal h2_4_OBUF : STD_LOGIC; 
  signal h2_5_OBUF : STD_LOGIC; 
  signal h2_6_OBUF : STD_LOGIC; 
  signal reset_IBUF : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal u3_Madd_n0009_inst_cy_1 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal u1_Ensec : STD_LOGIC; 
  signal u2_Min2_inst_cy_5 : STD_LOGIC; 
  signal u2_N2529 : STD_LOGIC; 
  signal CHOICE204 : STD_LOGIC; 
  signal u2_Enmin : STD_LOGIC; 
  signal u2_Min2_inst_sum_4 : STD_LOGIC; 
  signal u2_n0007 : STD_LOGIC; 
  signal u2_Min2_inst_cy_7 : STD_LOGIC; 
  signal u2_Madd_n0010_inst_cy_1 : STD_LOGIC; 
  signal u1_sec2_inst_cy_5 : STD_LOGIC; 
  signal u1_N2334 : STD_LOGIC; 
  signal CHOICE197 : STD_LOGIC; 
  signal u1_sec2_inst_sum_4 : STD_LOGIC; 
  signal u1_n0007 : STD_LOGIC; 
  signal u1_sec2_inst_cy_7 : STD_LOGIC; 
  signal u1_Madd_n0010_inst_cy_1 : STD_LOGIC; 
  signal u3_n0011 : STD_LOGIC; 
  signal u3_hou2_inst_cy_5 : STD_LOGIC; 
  signal CHOICE211 : STD_LOGIC; 
  signal CHOICE217 : STD_LOGIC; 
  signal u3_n0003 : STD_LOGIC; 
  signal u3_hou2_inst_cy_7 : STD_LOGIC; 
  signal N5109 : STD_LOGIC; 
  signal u3_n0010 : STD_LOGIC; 
  signal u3_n0010_SW0_O : STD_LOGIC; 
  signal u3_n0002_1_1_SW1_O : STD_LOGIC; 
  signal CHOICE183 : STD_LOGIC; 
  signal N5102 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_1 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_2 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_3 : STD_LOGIC; 
  signal GLOBAL_LOGIC0_4 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_1 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_2 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_3 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_4 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal Alarm_ENABLE : STD_LOGIC; 
  signal Alarm_TORGTS : STD_LOGIC; 
  signal Alarm_OUTMUX : STD_LOGIC; 
  signal s1_0_ENABLE : STD_LOGIC; 
  signal s1_0_TORGTS : STD_LOGIC; 
  signal s1_0_OUTMUX : STD_LOGIC; 
  signal s1_1_ENABLE : STD_LOGIC; 
  signal s1_1_TORGTS : STD_LOGIC; 
  signal s1_1_OUTMUX : STD_LOGIC; 
  signal s1_2_ENABLE : STD_LOGIC; 
  signal s1_2_TORGTS : STD_LOGIC; 
  signal s1_2_OUTMUX : STD_LOGIC; 
  signal m1_0_ENABLE : STD_LOGIC; 
  signal m1_0_TORGTS : STD_LOGIC; 
  signal m1_0_OUTMUX : STD_LOGIC; 
  signal s1_3_ENABLE : STD_LOGIC; 
  signal s1_3_TORGTS : STD_LOGIC; 
  signal s1_3_OUTMUX : STD_LOGIC; 
  signal Sec1_0_ENABLE : STD_LOGIC; 
  signal Sec1_0_TORGTS : STD_LOGIC; 
  signal Sec1_0_OUTMUX : STD_LOGIC; 
  signal m1_1_ENABLE : STD_LOGIC; 
  signal m1_1_TORGTS : STD_LOGIC; 
  signal m1_1_OUTMUX : STD_LOGIC; 
  signal s2_0_ENABLE : STD_LOGIC; 
  signal s2_0_TORGTS : STD_LOGIC; 
  signal s2_0_OUTMUX : STD_LOGIC; 
  signal s1_4_ENABLE : STD_LOGIC; 
  signal s1_4_TORGTS : STD_LOGIC; 
  signal s1_4_OUTMUX : STD_LOGIC; 
  signal Sec1_1_ENABLE : STD_LOGIC; 
  signal Sec1_1_TORGTS : STD_LOGIC; 
  signal Sec1_1_OUTMUX : STD_LOGIC; 
  signal m1_2_ENABLE : STD_LOGIC; 
  signal m1_2_TORGTS : STD_LOGIC; 
  signal m1_2_OUTMUX : STD_LOGIC; 
  signal s2_1_ENABLE : STD_LOGIC; 
  signal s2_1_TORGTS : STD_LOGIC; 
  signal s2_1_OUTMUX : STD_LOGIC; 
  signal s1_5_ENABLE : STD_LOGIC; 
  signal s1_5_TORGTS : STD_LOGIC; 
  signal s1_5_OUTMUX : STD_LOGIC; 
  signal Sec1_2_ENABLE : STD_LOGIC; 
  signal Sec1_2_TORGTS : STD_LOGIC; 
  signal Sec1_2_OUTMUX : STD_LOGIC; 
  signal m1_3_ENABLE : STD_LOGIC; 
  signal m1_3_TORGTS : STD_LOGIC; 
  signal m1_3_OUTMUX : STD_LOGIC; 
  signal s2_2_ENABLE : STD_LOGIC; 
  signal s2_2_TORGTS : STD_LOGIC; 
  signal s2_2_OUTMUX : STD_LOGIC; 
  signal s1_6_ENABLE : STD_LOGIC; 
  signal s1_6_TORGTS : STD_LOGIC; 
  signal s1_6_OUTMUX : STD_LOGIC; 
  signal Sec1_3_ENABLE : STD_LOGIC; 
  signal Sec1_3_TORGTS : STD_LOGIC; 
  signal Sec1_3_OUTMUX : STD_LOGIC; 
  signal m2_0_ENABLE : STD_LOGIC; 
  signal m2_0_TORGTS : STD_LOGIC; 
  signal m2_0_OUTMUX : STD_LOGIC; 
  signal m1_4_ENABLE : STD_LOGIC; 
  signal m1_4_TORGTS : STD_LOGIC; 
  signal m1_4_OUTMUX : STD_LOGIC; 
  signal s2_3_ENABLE : STD_LOGIC; 
  signal s2_3_TORGTS : STD_LOGIC; 
  signal s2_3_OUTMUX : STD_LOGIC; 
  signal m2_1_ENABLE : STD_LOGIC; 
  signal m2_1_TORGTS : STD_LOGIC; 
  signal m2_1_OUTMUX : STD_LOGIC; 
  signal m1_5_ENABLE : STD_LOGIC; 
  signal m1_5_TORGTS : STD_LOGIC; 
  signal m1_5_OUTMUX : STD_LOGIC; 
  signal s2_4_ENABLE : STD_LOGIC; 
  signal s2_4_TORGTS : STD_LOGIC; 
  signal s2_4_OUTMUX : STD_LOGIC; 
  signal m2_2_ENABLE : STD_LOGIC; 
  signal m2_2_TORGTS : STD_LOGIC; 
  signal m2_2_OUTMUX : STD_LOGIC; 
  signal m1_6_ENABLE : STD_LOGIC; 
  signal m1_6_TORGTS : STD_LOGIC; 
  signal m1_6_OUTMUX : STD_LOGIC; 
  signal s2_5_ENABLE : STD_LOGIC; 
  signal s2_5_TORGTS : STD_LOGIC; 
  signal s2_5_OUTMUX : STD_LOGIC; 
  signal m2_3_ENABLE : STD_LOGIC; 
  signal m2_3_TORGTS : STD_LOGIC; 
  signal m2_3_OUTMUX : STD_LOGIC; 
  signal s2_6_ENABLE : STD_LOGIC; 
  signal s2_6_TORGTS : STD_LOGIC; 
  signal s2_6_OUTMUX : STD_LOGIC; 
  signal m2_4_ENABLE : STD_LOGIC; 
  signal m2_4_TORGTS : STD_LOGIC; 
  signal m2_4_OUTMUX : STD_LOGIC; 
  signal m2_5_ENABLE : STD_LOGIC; 
  signal m2_5_TORGTS : STD_LOGIC; 
  signal m2_5_OUTMUX : STD_LOGIC; 
  signal m2_6_ENABLE : STD_LOGIC; 
  signal m2_6_TORGTS : STD_LOGIC; 
  signal m2_6_OUTMUX : STD_LOGIC; 
  signal h1_0_ENABLE : STD_LOGIC; 
  signal h1_0_TORGTS : STD_LOGIC; 
  signal h1_0_OUTMUX : STD_LOGIC; 
  signal h1_1_ENABLE : STD_LOGIC; 
  signal h1_1_TORGTS : STD_LOGIC; 
  signal h1_1_OUTMUX : STD_LOGIC; 
  signal h1_2_ENABLE : STD_LOGIC; 
  signal h1_2_TORGTS : STD_LOGIC; 
  signal h1_2_OUTMUX : STD_LOGIC; 
  signal h1_3_ENABLE : STD_LOGIC; 
  signal h1_3_TORGTS : STD_LOGIC; 
  signal h1_3_OUTMUX : STD_LOGIC; 
  signal h2_0_ENABLE : STD_LOGIC; 
  signal h2_0_TORGTS : STD_LOGIC; 
  signal h2_0_OUTMUX : STD_LOGIC; 
  signal h1_4_ENABLE : STD_LOGIC; 
  signal h1_4_TORGTS : STD_LOGIC; 
  signal h1_4_OUTMUX : STD_LOGIC; 
  signal h2_1_ENABLE : STD_LOGIC; 
  signal h2_1_TORGTS : STD_LOGIC; 
  signal h2_1_OUTMUX : STD_LOGIC; 
  signal h1_5_ENABLE : STD_LOGIC; 
  signal h1_5_TORGTS : STD_LOGIC; 
  signal h1_5_OUTMUX : STD_LOGIC; 
  signal h2_2_ENABLE : STD_LOGIC; 
  signal h2_2_TORGTS : STD_LOGIC; 
  signal h2_2_OUTMUX : STD_LOGIC; 
  signal h1_6_ENABLE : STD_LOGIC; 
  signal h1_6_TORGTS : STD_LOGIC; 
  signal h1_6_OUTMUX : STD_LOGIC; 
  signal hou1_0_ENABLE : STD_LOGIC; 
  signal hou1_0_TORGTS : STD_LOGIC; 
  signal hou1_0_OUTMUX : STD_LOGIC; 
  signal h2_3_ENABLE : STD_LOGIC; 
  signal h2_3_TORGTS : STD_LOGIC; 
  signal h2_3_OUTMUX : STD_LOGIC; 
  signal hou1_1_ENABLE : STD_LOGIC; 
  signal hou1_1_TORGTS : STD_LOGIC; 
  signal hou1_1_OUTMUX : STD_LOGIC; 
  signal h2_4_ENABLE : STD_LOGIC; 
  signal h2_4_TORGTS : STD_LOGIC; 
  signal h2_4_OUTMUX : STD_LOGIC; 
  signal sec2_0_ENABLE : STD_LOGIC; 
  signal sec2_0_TORGTS : STD_LOGIC; 
  signal sec2_0_OUTMUX : STD_LOGIC; 
  signal hou1_2_ENABLE : STD_LOGIC; 
  signal hou1_2_TORGTS : STD_LOGIC; 
  signal hou1_2_OUTMUX : STD_LOGIC; 
  signal h2_5_ENABLE : STD_LOGIC; 
  signal h2_5_TORGTS : STD_LOGIC; 
  signal h2_5_OUTMUX : STD_LOGIC; 
  signal sec2_1_ENABLE : STD_LOGIC; 
  signal sec2_1_TORGTS : STD_LOGIC; 
  signal sec2_1_OUTMUX : STD_LOGIC; 
  signal hou1_3_ENABLE : STD_LOGIC; 
  signal hou1_3_TORGTS : STD_LOGIC; 
  signal hou1_3_OUTMUX : STD_LOGIC; 
  signal h2_6_ENABLE : STD_LOGIC; 
  signal h2_6_TORGTS : STD_LOGIC; 
  signal h2_6_OUTMUX : STD_LOGIC; 
  signal sec2_2_ENABLE : STD_LOGIC; 
  signal sec2_2_TORGTS : STD_LOGIC; 
  signal sec2_2_OUTMUX : STD_LOGIC; 
  signal hou2_0_ENABLE : STD_LOGIC; 
  signal hou2_0_TORGTS : STD_LOGIC; 
  signal hou2_0_OUTMUX : STD_LOGIC; 
  signal sec2_3_ENABLE : STD_LOGIC; 
  signal sec2_3_TORGTS : STD_LOGIC; 
  signal sec2_3_OUTMUX : STD_LOGIC; 
  signal hou2_1_ENABLE : STD_LOGIC; 
  signal hou2_1_TORGTS : STD_LOGIC; 
  signal hou2_1_OUTMUX : STD_LOGIC; 
  signal hou2_2_ENABLE : STD_LOGIC; 
  signal hou2_2_TORGTS : STD_LOGIC; 
  signal hou2_2_OUTMUX : STD_LOGIC; 
  signal hou2_3_ENABLE : STD_LOGIC; 
  signal hou2_3_TORGTS : STD_LOGIC; 
  signal hou2_3_OUTMUX : STD_LOGIC; 
  signal min1_0_ENABLE : STD_LOGIC; 
  signal min1_0_TORGTS : STD_LOGIC; 
  signal min1_0_OUTMUX : STD_LOGIC; 
  signal min1_1_ENABLE : STD_LOGIC; 
  signal min1_1_TORGTS : STD_LOGIC; 
  signal min1_1_OUTMUX : STD_LOGIC; 
  signal min1_2_ENABLE : STD_LOGIC; 
  signal min1_2_TORGTS : STD_LOGIC; 
  signal min1_2_OUTMUX : STD_LOGIC; 
  signal min1_3_ENABLE : STD_LOGIC; 
  signal min1_3_TORGTS : STD_LOGIC; 
  signal min1_3_OUTMUX : STD_LOGIC; 
  signal min2_0_ENABLE : STD_LOGIC; 
  signal min2_0_TORGTS : STD_LOGIC; 
  signal min2_0_OUTMUX : STD_LOGIC; 
  signal min2_1_ENABLE : STD_LOGIC; 
  signal min2_1_TORGTS : STD_LOGIC; 
  signal min2_1_OUTMUX : STD_LOGIC; 
  signal min2_2_ENABLE : STD_LOGIC; 
  signal min2_2_TORGTS : STD_LOGIC; 
  signal min2_2_OUTMUX : STD_LOGIC; 
  signal min2_3_ENABLE : STD_LOGIC; 
  signal min2_3_TORGTS : STD_LOGIC; 
  signal min2_3_OUTMUX : STD_LOGIC; 
  signal reset_IBUF_0 : STD_LOGIC; 
  signal u3_Madd_n0009_inst_lut2_01_O : STD_LOGIC; 
  signal u3_n0009_1_CYMUXG : STD_LOGIC; 
  signal u3_n0009_1_XORG : STD_LOGIC; 
  signal u3_n0009_1_GROM : STD_LOGIC; 
  signal u3_Madd_n0009_inst_cy_0 : STD_LOGIC; 
  signal u3_n0009_1_LOGIC_ZERO : STD_LOGIC; 
  signal u3_n0009_2_LOGIC_ZERO : STD_LOGIC; 
  signal u3_n0009_2_FROM : STD_LOGIC; 
  signal u3_n0009_2_XORF : STD_LOGIC; 
  signal u3_n0009_2_XORG : STD_LOGIC; 
  signal u3_Hou1_3_rt : STD_LOGIC; 
  signal u3_Madd_n0009_inst_cy_2 : STD_LOGIC; 
  signal u3_n0009_2_CYINIT : STD_LOGIC; 
  signal u2_n0004_SW113_O : STD_LOGIC; 
  signal u2_Enmin_CYMUXG : STD_LOGIC; 
  signal u2_Enmin_XORG : STD_LOGIC; 
  signal u2_Min2_inst_lut3_01_O : STD_LOGIC; 
  signal u2_Min2_inst_cy_4 : STD_LOGIC; 
  signal u2_Enmin_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u2_Enmin_LOGIC_ZERO : STD_LOGIC; 
  signal u2_Min2_1_FFY_RST : STD_LOGIC; 
  signal u2_Min2_1_FFX_RST : STD_LOGIC; 
  signal u2_Min2_1_FROM : STD_LOGIC; 
  signal u2_Min2_inst_sum_5 : STD_LOGIC; 
  signal u2_Min2_1_CYMUXG : STD_LOGIC; 
  signal u2_Min2_1_LOGIC_ZERO : STD_LOGIC; 
  signal u2_Min2_inst_lut3_21_O : STD_LOGIC; 
  signal u2_Min2_inst_cy_6 : STD_LOGIC; 
  signal u2_Min2_1_CYINIT : STD_LOGIC; 
  signal u2_Min2_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u2_Min2_inst_sum_6 : STD_LOGIC; 
  signal u2_Min2_3_FFX_RST : STD_LOGIC; 
  signal u2_Min2_3_rt : STD_LOGIC; 
  signal u2_Min2_inst_sum_7 : STD_LOGIC; 
  signal u2_Min2_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u2_Min2_3_CYINIT : STD_LOGIC; 
  signal u2_Madd_n0010_inst_lut2_01_O : STD_LOGIC; 
  signal u2_n0010_1_CYMUXG : STD_LOGIC; 
  signal u2_n0010_1_XORG : STD_LOGIC; 
  signal u2_n0010_1_GROM : STD_LOGIC; 
  signal u2_Madd_n0010_inst_cy_0 : STD_LOGIC; 
  signal u2_n0010_1_LOGIC_ZERO : STD_LOGIC; 
  signal u2_n0010_2_LOGIC_ZERO : STD_LOGIC; 
  signal u2_n0010_2_FROM : STD_LOGIC; 
  signal u2_n0010_2_XORF : STD_LOGIC; 
  signal u2_n0010_2_XORG : STD_LOGIC; 
  signal u2_Min1_3_rt : STD_LOGIC; 
  signal u2_Madd_n0010_inst_cy_2 : STD_LOGIC; 
  signal u2_n0010_2_CYINIT : STD_LOGIC; 
  signal u1_n0004_SW113_O : STD_LOGIC; 
  signal u1_Ensec_CYMUXG : STD_LOGIC; 
  signal u1_Ensec_XORG : STD_LOGIC; 
  signal u1_sec2_inst_lut3_01_O : STD_LOGIC; 
  signal u1_sec2_inst_cy_4 : STD_LOGIC; 
  signal u1_Ensec_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u1_Ensec_LOGIC_ZERO : STD_LOGIC; 
  signal u1_sec2_1_FFY_RST : STD_LOGIC; 
  signal u1_sec2_1_FROM : STD_LOGIC; 
  signal u1_sec2_inst_sum_5 : STD_LOGIC; 
  signal u1_sec2_1_CYMUXG : STD_LOGIC; 
  signal u1_sec2_1_LOGIC_ZERO : STD_LOGIC; 
  signal u1_sec2_inst_lut3_21_O : STD_LOGIC; 
  signal u1_sec2_inst_cy_6 : STD_LOGIC; 
  signal u1_sec2_1_CYINIT : STD_LOGIC; 
  signal u1_sec2_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u1_sec2_inst_sum_6 : STD_LOGIC; 
  signal u1_sec2_3_rt : STD_LOGIC; 
  signal u1_sec2_inst_sum_7 : STD_LOGIC; 
  signal u1_sec2_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u1_sec2_3_CYINIT : STD_LOGIC; 
  signal u1_Madd_n0010_inst_lut2_01_O : STD_LOGIC; 
  signal u1_n0010_1_CYMUXG : STD_LOGIC; 
  signal u1_n0010_1_XORG : STD_LOGIC; 
  signal u1_n0010_1_GROM : STD_LOGIC; 
  signal u1_Madd_n0010_inst_cy_0 : STD_LOGIC; 
  signal u1_n0010_1_LOGIC_ZERO : STD_LOGIC; 
  signal u1_n0010_2_LOGIC_ZERO : STD_LOGIC; 
  signal u1_n0010_2_FROM : STD_LOGIC; 
  signal u1_n0010_2_XORF : STD_LOGIC; 
  signal u1_n0010_2_XORG : STD_LOGIC; 
  signal u1_Sec1_3_rt : STD_LOGIC; 
  signal u1_Madd_n0010_inst_cy_2 : STD_LOGIC; 
  signal u1_n0010_2_CYINIT : STD_LOGIC; 
  signal u3_hou2_0_FFY_RST : STD_LOGIC; 
  signal u3_hou2_0_FROM : STD_LOGIC; 
  signal u3_hou2_0_CYMUXG : STD_LOGIC; 
  signal u3_hou2_0_GROM : STD_LOGIC; 
  signal u3_hou2_inst_cy_4 : STD_LOGIC; 
  signal u3_hou2_0_LOGIC_ZERO : STD_LOGIC; 
  signal u3_hou2_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u3_hou2_inst_sum_4 : STD_LOGIC; 
  signal u3_hou2_1_FFX_RST : STD_LOGIC; 
  signal u3_hou2_1_FFY_RST : STD_LOGIC; 
  signal u3_hou2_inst_lut3_11_O : STD_LOGIC; 
  signal u3_hou2_inst_sum_5 : STD_LOGIC; 
  signal u3_hou2_1_CYMUXG : STD_LOGIC; 
  signal u3_hou2_1_LOGIC_ZERO : STD_LOGIC; 
  signal u3_hou2_1_GROM : STD_LOGIC; 
  signal u3_hou2_inst_cy_6 : STD_LOGIC; 
  signal u3_hou2_1_CYINIT : STD_LOGIC; 
  signal u3_hou2_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u3_hou2_inst_sum_6 : STD_LOGIC; 
  signal u3_hou2_3_FFX_RST : STD_LOGIC; 
  signal u3_hou2_3_rt : STD_LOGIC; 
  signal u3_hou2_inst_sum_7 : STD_LOGIC; 
  signal u3_hou2_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u3_hou2_3_CYINIT : STD_LOGIC; 
  signal u2_Min1_3_FFY_RST : STD_LOGIC; 
  signal u2_n0003_3_1_O : STD_LOGIC; 
  signal u2_Min1_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u2_n0003_2_1_O : STD_LOGIC; 
  signal u1_n0003_3_1_O : STD_LOGIC; 
  signal u1_Sec1_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u1_n0003_2_1_O : STD_LOGIC; 
  signal u3_Hou1_2_FROM : STD_LOGIC; 
  signal u3_Hou1_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u3_n0002_2_1_O : STD_LOGIC; 
  signal u3_Hou1_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u3_n0002_3_1_O : STD_LOGIC; 
  signal u3_n0010_SW0_O_FROM : STD_LOGIC; 
  signal u3_n0010_SW0_O_GROM : STD_LOGIC; 
  signal CHOICE217_FROM : STD_LOGIC; 
  signal CHOICE217_GROM : STD_LOGIC; 
  signal h2_6_OBUF_FROM : STD_LOGIC; 
  signal h2_6_OBUF_GROM : STD_LOGIC; 
  signal h2_0_OBUF_FROM : STD_LOGIC; 
  signal h2_0_OBUF_GROM : STD_LOGIC; 
  signal u2_Min1_0_BXMUXNOT : STD_LOGIC; 
  signal u2_Min1_0_FROM : STD_LOGIC; 
  signal u2_Min1_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u2_n0003_1_1_O : STD_LOGIC; 
  signal m1_1_OBUF_FROM : STD_LOGIC; 
  signal m1_1_OBUF_GROM : STD_LOGIC; 
  signal u2_Min2_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u1_n0007_FROM : STD_LOGIC; 
  signal u1_n0007_GROM : STD_LOGIC; 
  signal s1_6_OBUF_FROM : STD_LOGIC; 
  signal s1_6_OBUF_GROM : STD_LOGIC; 
  signal s1_5_OBUF_FROM : STD_LOGIC; 
  signal s1_5_OBUF_GROM : STD_LOGIC; 
  signal CHOICE197_FROM : STD_LOGIC; 
  signal CHOICE197_GROM : STD_LOGIC; 
  signal u1_Sec1_0_BXMUXNOT : STD_LOGIC; 
  signal u1_Sec1_0_FROM : STD_LOGIC; 
  signal u1_Sec1_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u1_n0003_1_1_O : STD_LOGIC; 
  signal m1_5_OBUF_FROM : STD_LOGIC; 
  signal m1_5_OBUF_GROM : STD_LOGIC; 
  signal m1_6_OBUF_FROM : STD_LOGIC; 
  signal m1_6_OBUF_GROM : STD_LOGIC; 
  signal s1_4_OBUF_FROM : STD_LOGIC; 
  signal s1_4_OBUF_GROM : STD_LOGIC; 
  signal u3_Hou1_0_BXMUXNOT : STD_LOGIC; 
  signal u3_Hou1_0_FROM : STD_LOGIC; 
  signal u3_Hou1_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal u3_n0002_1_1_O : STD_LOGIC; 
  signal CHOICE204_FROM : STD_LOGIC; 
  signal CHOICE204_GROM : STD_LOGIC; 
  signal s2_6_OBUF_FROM : STD_LOGIC; 
  signal s2_6_OBUF_GROM : STD_LOGIC; 
  signal CHOICE211_FROM : STD_LOGIC; 
  signal CHOICE211_GROM : STD_LOGIC; 
  signal m1_4_OBUF_FROM : STD_LOGIC; 
  signal m1_4_OBUF_GROM : STD_LOGIC; 
  signal s2_4_OBUF_FROM : STD_LOGIC; 
  signal s2_4_OBUF_GROM : STD_LOGIC; 
  signal m1_3_OBUF_GROM : STD_LOGIC; 
  signal h2_1_OBUF_FROM : STD_LOGIC; 
  signal h2_1_OBUF_GROM : STD_LOGIC; 
  signal N5102_FROM : STD_LOGIC; 
  signal N5102_GROM : STD_LOGIC; 
  signal u1_sec2_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal m2_6_OBUF_FROM : STD_LOGIC; 
  signal m2_6_OBUF_GROM : STD_LOGIC; 
  signal s2_5_OBUF_FROM : STD_LOGIC; 
  signal s2_5_OBUF_GROM : STD_LOGIC; 
  signal m2_5_OBUF_FROM : STD_LOGIC; 
  signal m2_5_OBUF_GROM : STD_LOGIC; 
  signal m2_4_OBUF_FROM : STD_LOGIC; 
  signal m2_4_OBUF_GROM : STD_LOGIC; 
  signal h1_3_OBUF_FROM : STD_LOGIC; 
  signal h1_3_OBUF_GROM : STD_LOGIC; 
  signal h1_6_OBUF_FROM : STD_LOGIC; 
  signal h1_6_OBUF_GROM : STD_LOGIC; 
  signal h1_5_OBUF_FROM : STD_LOGIC; 
  signal h1_5_OBUF_GROM : STD_LOGIC; 
  signal N5109_GROM : STD_LOGIC; 
  signal u2_Min1_0_FFY_RST : STD_LOGIC; 
  signal u2_Min1_0_FFX_RST : STD_LOGIC; 
  signal u2_Min2_0_FFY_RST : STD_LOGIC; 
  signal u1_Sec1_0_FFY_RST : STD_LOGIC; 
  signal u2_Enmin_FFX_RST : STD_LOGIC; 
  signal u2_Min1_3_FFX_RST : STD_LOGIC; 
  signal u1_Sec1_3_FFY_RST : STD_LOGIC; 
  signal u1_Sec1_3_FFX_RST : STD_LOGIC; 
  signal u3_Hou1_2_FFY_RST : STD_LOGIC; 
  signal u3_Hou1_3_FFY_RST : STD_LOGIC; 
  signal u1_Ensec_FFX_RST : STD_LOGIC; 
  signal u1_sec2_1_FFX_RST : STD_LOGIC; 
  signal u1_sec2_3_FFX_RST : STD_LOGIC; 
  signal u1_Sec1_0_FFX_RST : STD_LOGIC; 
  signal u3_Hou1_0_FFY_RST : STD_LOGIC; 
  signal u3_Hou1_0_FFX_RST : STD_LOGIC; 
  signal u1_sec2_0_FFY_RST : STD_LOGIC; 
  signal clk_BUFGP_BUFG_CE : STD_LOGIC; 
  signal PWR_GND_0_FROM : STD_LOGIC; 
  signal PWR_GND_0_GROM : STD_LOGIC; 
  signal PWR_GND_1_GROM : STD_LOGIC; 
  signal PWR_GND_2_GROM : STD_LOGIC; 
  signal PWR_GND_3_FROM : STD_LOGIC; 
  signal PWR_GND_3_GROM : STD_LOGIC; 
  signal PWR_GND_4_FROM : STD_LOGIC; 
  signal PWR_GND_4_GROM : STD_LOGIC; 
  signal PWR_GND_5_FROM : STD_LOGIC; 
  signal PWR_GND_5_GROM : STD_LOGIC; 
  signal PWR_VCC_0_FROM : STD_LOGIC; 
  signal PWR_VCC_1_FROM : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal u1_Sec1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal u3_Hou1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal u1_sec2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal u3_hou2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal u2_Min1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal u2_Min2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal u3_n0009 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal u2_n0010 : STD_LOGIC_VECTOR ( 3 downto 1 );